Research

Project Artemis (09/2021 – 12/2023)

The VCAS Lab is involved with the Project Artemis, which is entitled as “Securing Supply Chain Traceability Using Distributed and Embedded Security Mechanims”. The Project, whose Primary Investigator for the University of Ioannina is Asst. Prof. Vasileios Tenentes, focuses on evaluating the traceability capabilities on different supply chain networks and, then, proposing distributed as well as embedded system architectures for securing the traceability of supply chain products and assets. The project involves three Academic institutions (the University of Ioannina, the University of Piraeus and the University of Thessaly) and two companies. The first company, itrack (https://www.itrack.gr), develops systems for tracking supply chain logistics. The second company, the Floridis AEVEK, is the main supplier for the cold supply chain products at the largest supermarket chains that are active in Greece, such as Carrefur, AB Vasilopoulos, Lidl, Makro, Metro, and the Olympic Catering, to name a few; the company manages a huge fleet of chiller lorries and storage units for the cold supply chain. The Project is co‐financed by the European Regional Development Fund of the European Union and Greek national funds through the Operational Program Competitiveness, Entrepreneurship and Innovation, under the call RESEARCH – CREATE – INNOVATE (project code:Τ2EDK-02836. Grant: 996,650 €.

 

Past Research Projects in which VCAS Lab Members were involved (reverse chronological order)

  1. VIOLIN – 2018-2022 (source: NSF and ESF)
  2. UniServer (source: ESF)
  3. PRiME: Power-efficient, Reliable, Many-core Embedded systems (source: EPSRC)
  4. RHEA: Resilient Hardware for Energy-efficient Applications (source: EPSRC)
    Dr Tenentes is a member of the RHEA team that has collaborated on resilient hardware for energy-efficient applications, which has been funded by EPSRC as the Resilient-Project.
    The Resilient-Project outcomes have already been cited by a numerous prestigious publications in IEEE Conferences & Transactions, and the prestigious IEEE Spectrum Magazine.Our research was validated using chips provided by ARM Ltd, which was one of our industrial patterns.
  5. REIN – Thallis (source: NSF and ESF)
  6. Heracletus II (source: NSF and ESF)
  7. Pythagoras (source: NSF and ESF)

Journals

  1. V. Gerakis, Y. Tsiatouhas and A.  Hatzopoulos, “A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs”, Springer, Journal of Electronic Testing: Theory and Applications, vol. 37, pp. 191-203, 2021.
  2. H-M. Dounavi, S. Sfikas and Y. Tsiatouhas, “Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier”, Springer, Journal of Electronic Testing: Theory and Applications, vol. 37, pp. 65-82, 2021.
  3. H-M. Dounavi, S. Sfikas and Y. Tsiatouhas, “Periodic Monitoring of BTI Induced Aging in SRAM Sense Amplifiers”, IEEE Transactions on Device and Materials Reliability, vol. 19, no. 1, pp. 64-72, 2019.
  4. Tenentes, Vasileios, Rossi, Daniele, K. Chakrabarty, B. M. Al-Hashimi, (2017) Leakage Current Analysis for Diagnosis of Power Gated Designs with Bridge Defect, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. PP, no. 99, pp. 1-1.
  5. J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “State Reduction for Efficient Digital Calibration of Analog/RF Integrated Circuits”, Springer, Analog Integrated Circuits and Signal Processing, vol. 90, no. 1, pp. 65-79, 2017.
  6. Daniele Rossi, Vasileios Tenentes, S. M. Reddy and B. M. Al-Hashimi, H. A. Brown, (2017) Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, pp. 1-1.
  7. D. Gutierrez, Mauricio Tenentes, Vasileios, D. Rossi, Kazmierski, Tom J., (2017) Susceptible Workload Evaluation and Protection using Selective Fault Tolerance, in Journal of Electronic Testing, Springer.
  8. Rossi, Daniele, Tenentes, Vasileios, Yang, Sheng, Khursheed, Saqib and Al-Hashimi, Bashir (2016) Aging benefits in nanometer CMOS designs. IEEE Transactions on Circuits and Systems II Express Briefs, doi: 10.1109/TCSII.2016.2561206.
  9. Y. Sfikas and Y. Tsiatouhas, “”Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs“,” IEEE Transactions on Computers, vol. 65, no. 7, pp. 2339-2345, 2016.
  10. S. Valadimas, Y. Tsiatouhas and A. Arapoyanni, ““Timing Error Tolerance in Small Core Designs for SoC Applications”,” IEEE Transactions on Computers, vol. 65, no.2, pp. 654-663, 2016.
  11. Tenentes, Vasileios, Rossi, Daniele, Yang, Sheng, Khursheed, Saqib, Al-Hashimi, Bashir M. and Gunn, Steve R. (2016) Coarse-grained Online Monitoring of BTI Aging by Reusing Power Gating Infrastructure. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, accepted.
  12. Halak, Basel, Tenentes, Vasileios, Rossi, Daniele, (2016) The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology, Microelectronics Reliability, Elsevier,\\doi:10.1016/j.microrel.2016.10.018, early access.
  13. Rossi, Daniele, Tenentes, Vasileios, Yang, Sheng, Khursheed, Saqib and Al-Hashimi, Bashir (2015) Reliable power gating with NBTI aging benefits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 8, pp. 2735-2744.
  14. Tenentes, Vasileios, Khursheed, Saqib, Rossi, Daniele, Yang, Sheng and Al-Hashimi, Bashir M. (2015) DFT architecture with power-distribution-network consideration for delay-based power gating test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 12, pp. 2013-2024.
  15. • K. Katsarou and Y. Tsiatouhas, ““Soft Error Interception Latch: A Double Node Charge Sharing SEU Tolerant Design”,” IET Electronics Letters, vol. 51, no. 4, pp. 330-332, 2015.
  16. • S. Matakias, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, “”A Current Monitoring Technique for IDDQ Testing in Digital Integrated Circuits”,” Elsevier, Integration the VLSI Journal, vol. 50, no. 1, pp. 48-60, 2015.
  17. • R. Wang, Z. Zang, X. Kavousianos, Y. Tsiatouhas and K. Chakrabarty, “”Built-In Self-Test, Diagnosis and Repair of Multi-Mode Power Switches”,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no.8, pp. 1231-1244, 2014.
  18. E. Arvaniti and Y. Tsiatouhas, “”Low Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique”,” Springer Journal of Electronic Testing: Theory and Applications, vol. 30, pp. 329-341, 2014.
  19. • Y. Sfikas, Y. Tsiatouhas and S. Hamdioui, “”Layout-Based Refined NPSF Model for DRAM Characterization and Testing”,” IEEE Transactions on VLSI Systems, vol. 22, no. 6, pp. 1446-1450, 2014.
  20. • S. Valadimas, A. Floros, Y. Tsiatouhas, A. Arapoyanni and X. Kavousianos, “”The Time Dilation Technique for Timing Error Tolerance”,” IEEE Transactions on Computers, vol. 63, no.5, pp. 1277-1286, 2014.
  21. • Z. Zang, X. Kavousianos, K. Chakrabarty and Y. Tsiatouhas, “”Static Power Reduction using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches”,” IEEE Transactions on VLSI Systems, vol. 22, no. 1, pp. 13-26, 2014.
  22.  S. Valadimas, Y. Tsiatouhas, A. Arapoyanni and P. Xarchakos, “”Effective Timing Error Tolerance in Flip-Flop Based Core Designs”,” Springer Journal of Electronic Testing: Theory and Applications, vol. 29, pp. 795-804, 2013.
  23. • C. Efstathiou, Z. Owda and Y. Tsiatouhas, “”New High Speed Multi-Output Carry Look-Ahead Adders”,” IEEE Transactions on Circuits and Systems-II, vol. 60, no. 10, pp. 667-671, 2013.
  24. • J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “”Adjustable RF Mixers’ Alternate Test Efficiency Optimization by the Reduction of Test Observables”,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no.9, pp. 1383-1394, 2013.
  25. • J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “”A Test and Calibration Strategy for Adjustable RF Circuits”,” Springer, Analog Integrated Circuits and Signal Processing, vol. 74, no.1, pp. 175-192, 2013.
  26. • J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “”A Bult-In Voltage Measurement Technique for the Calibration of RF Mixers”,” IEEE Transactions on Instrumentation and Measurement, vol. 62, no.4, pp. 732-742, 2013.
  27. V. Tenentes and X. Kavousianos, “High-Quality Statistical Test-Compression with Narrow ATE Interface”, in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2013.
  28. X. Kavousianos, V. Tenentes, K. Chakrabarty, and M. Kalligeros, “Defect-oriented LFSR reseeding to target unmodeled defects using stuck-at test sets”, accepted for publication in IEEE Transactions on VLSI Systems, 2011.
  29. • L. Dermentzoglou, A. Arapoyanni and Y. Tsiatouhas, “”A Bult-In-Test Circuit for RF Differential Low Noise Amplifiers”,” IEEE Transactions on Circuits and Systems – I, vol. 57, no.7, pp. 1549-1558, 2010.
  30. V. Tenentes, X. Kavousianos and E. Kalligeros, “Single and Variable State Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1640-1644, Oct. 2010.
  31. • S. Matakias, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, ““A Current Mode, Parallel, Two-Rail Code Checker”,” IEEE Transactions on Computers, vol. 57, no.8, pp. 1032-1045, 2008.
  32. • Th. Haniotakis, Y. Tsiatouhas, D. Nikolos and C. Efstathiou, “”Testable Designs of Multiple Precharged Domino Circuits”,” IEEE Transactions on VLSI Systems, vol. 15, no. 4, pp. 461-465, 2007.
  33. • Y. Tsiatouhas, “”A Stress-Relaxed Negative Voltage-Level Converter”,” IEEE Transactions on Circuits and Systems – II, vol. 54, no. 3, pp. 282-286, 2007.
  34. • K. Limniotis, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “”A Design Technique for Energy Reduction in NORA CMOS Logic”,” IEEE Transactions on Circuits and Systems – I, vol. 53, no. 12, pp. 2647-2655, 2006.
  35. • S. Matakias, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “”A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs”,” Journal of Electronic Testing: Theory and Applications, vol. 20, no. 5, pp. 517-525, 2004.
  36. • L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “”A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators”,” Journal of Electronic Testing: Theory and Applications, vol. 20, no. 2, pp. 133-142, 2004.
  37. • Th. Haniotakis, Y. Tsiatouhas, C. Efstathiou and D. Nikolos, “”Domino-CMOS Strongly Code Disjpoint and Strongly Fault Secure 2-out-of-3 and 1-out-of-3 Code Checkers”,” International Journal of Electronics, vol. 90, no.2, pp. 145-158, 2003.
  38. • Y. Tsiatouhas, Y. Moisiadis, Th. Haniotakis, D. Nikolos and A. Arapoyanni, “”A New Technique for IDDQ Testing in Nanometer Technologies”,” Integration the VLSI Journal, vol. 31, pp. 183-194, 2002.
  39. • A. Chrisanthopoulos, Y. Moisiadis, Y. Tsiatouhas and A. Arapoyanni, ““Comparative Study of Different Current Mode Sense Amplifiers in Submicron CMOS Technology”,” IEE Proceedings on Circuits, Devices and Systems, vol. 149, no. 3, pp. 154-158, 2002.
  40. • H.T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos and M. Nicolaidis, “”On Path Delay Fault Testing of Multiplexer-Based Shifters”,” International Journal of Electronics, vol. 88, no. 8, pp. 923-937, 2001.
  41. • G. Kamoulakos, Y. Tsiatouhas, A. Chrisanthopoulos and A. Arapoyianni, “”A High –Density DRAM Cell with Built-In Gain Stage”,” IEEE Transactions on Electron Devices, vol. 48, no. 6, pp. 1194-1199, 2001.
  42. • G. Kamoulakos, Th. Haniotakis, Y. Tsiatouhas, J-P. Schoellkopf and A. Arapoyianni, “”Device Simulation of an n-DMOS Cell with Trench Isolation”,” Microelectronics Journal, vol. 32 (1), pp. 75-80, 2001.
  43. • G. Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas and A. Arapoyanni, ““Management of Charge Pump Circuits”,” Integration the VLSI Journal, vol. 30 (1), pp. 91-101, 2000.
  44.  Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, A Paschalis and C. Halatsis, “”Hierarchical Robust Test Generation for CMOS Circuit Stuck-Open Faults”,” International Journal of Electronics, vol. 82, no. 1, pp. 45-60, 1997.
  45. • Y. Tsiatouhas, Th. Haniotakis, C. Halatsis and A. Arapoyanni, “”Design of Stuck-Open Fault Testable CMOS Complex Gates”,” IEE Electronics Letters, vol. 32, no. 4, pp. 315-317, 1996.
  46. • Y. Tsiatouhas, A. Paschalis, D. Nikolos and C. Halatsis, “”Robust Test Generation for Transistor Stuck-Open Faults in CMOS Complex Gates”,” International Journal of Electronics, vol. 79, no. 2, pp. 129-142, 1995.

Book Chapters

  1. H-M. Dounavi, S. Sfikas and Y. Tsiatouhas, “Aging Monitors for SRAM Memory Cells and Sense Amplifiers,” Chapter in the Book: Ageing of Integrated Circuits: Causes, Effects and Mitigation Techniques, editor: Basel Halak, Springer, ISBN: 978-3-030-23780-6, 2020.
  2. J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “Machine Learning in Alternate Testing of Integrated Circuits,” Chapter in the Book: Machine Learning Paradigms: Applications of Learning and Analytics in Intelligent Systems, editors: George A. Tsihrintzis, Maria Virvou, Lakhmi C. Jain, Springer, ISBN: 978-3-030-15627-5, 2019.
  3. V. Tenentes and X. Kavousianos “Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing”, Chapter in the Book: Designing Very Large Scale Integration Systems: Emerging Trends & Challenges, editors: N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Springer, ISBN: -, 2011.
  4. A. Floros, Y. Tsiatouhas and X. Kavousianos, “Timing Error Detection and Correction by Time Dilation,” Chapter in the Book: VLSI-SoC: Design Methodologies for SoC and SiP, editors: C. Piguet, R. Reis, D. Soudris, Springer, ISBN: 978-3-642-12266-8, 2010.

Conferences

  1. Tenentes, Vasileios, Leech, Charles, Bragg, Graeme, Merrett, Geoffrey, Al-Hashimi, Bashir, Amrouch, Hussam, Henkel, Jörg and Das, Shidhartha (2017) Hardware and software innovations in energy-efficient system-reliability monitoring In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. IEEE. 5 pp.
  2. Gutierrez Alcala, Mauricio, Daniel, Tenentes, Vasileios, Kazmierski, Tomasz and Rossi, Daniele (2017) Low cost error monitoring for improved maintainability of IoT applications At IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. 23 – 25 Oct 2017. 6 pp.
  3. D. Gutierrez, Mauricio, Tenentes, Vasileios, Rossi, Daniele, Kazmierski, Tom J., Concurrent Detection of Systematic Errors for Low Power Non-safety Critical Applications, submitted to 22nd IEEE European Test Symposium (ETS), 2017
  4. Chahal, Hardeep, Tenentes, Vasileios, Rossi, Daniele and Al-Hashimi, Bashir M. (2016) BTI aware thermal management for reliable DVFS designs. In, Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium (DFT’16), Connecticut, US, 19 – 20 Sep 2016. 6pp. (best paper award nominee)
  5. D. Gutierrez, Mauricio, Tenentes, Vasileios, Kazmierski, Tom J., (2016) Susceptible Workload driven Selective Fault Tolerance using a Probabilistic Fault Model, accepted at, 22nd IEEE International On-Line Testing Symposium, Spain, 04 – 06 Jul 2016. 6pp.
  6. Rossi, Daniele, Tenentes, Vasileios, Khursheed, Saqib and Al-Hashimi, Bashir M. (2015) BTI and leakage aware dynamic voltage scaling for reliable low power cache memories. In, 21st IEEE International On-Line Testing Symposium, Halkidiki, Greece, 06 – 08 Jul 2015. 6pp.
  7. Tenentes, Vasileios, Rossi, Daniele, Khursheed, Saqib and Al-Hashimi, Bashir M. (2015) Diagnosis of power switches with power-distribution-network consideration. In, 20th IEEE European Test Symposium (ETS 2015), Cluj-Napoca, RO, 25 – 29 May 2015. 6pp.
  8. Rossi, Daniele, Tenentes, Vasileios, Khursheed, Saqib and Al-Hashimi, Bashir (2015) NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating. In, IEEE European Test Symposium 2015, Cluj-Napoca, RO, 25 – 29 May 2015. 6pp.
  9. Tenentes, Vasileios, Khursheed, Syed Saqib, Al-Hashimi, Bashir M., Zhong, Shida and Yang, Sheng (2014) High quality testing of grid style power gating. In, 23rd Asian Test Symposium (ATS), Hangzhou, CN, 16 – 19 Nov 2014. 6pp.
  10. V. Tenentes and X. Kavousianos, “Test-Data Volume and Scan-Power Reduction with Low ATE Interface for Multi-Core SoCs”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), session 10B, San Jose, Nov. 2011
  11. V. Tenentes and X. Kavousianos, “Low Power Test-Compression for High Test-Quality and Low Test-Data Volume”, 20th IEEE Asian Test Symposium (ATS), session A2, New Delhi, Nov. 2011
  12. S. Balatsouka, V. Tenentes and X. Kavousianos and K. Chakrabarty, “Defect Aware X-Filling for Low-Power Scan Testing”, IEEE/ACM Design, Automation & Test in Europe (DATE) Conference, pp. 873-878, March 2010.
  13. V. Tenentes and X. Kavousianos, “Self-Freeze Linear Decompressors for Low Power Testing”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 63-68, July 2010.
  14. X. Kavousianos, K. Chakrabarty, E. Kalligeros and V. Tenentes, “Defect coverage-driven window-based test compression”, 19th IEEE Asian Test Symposium (ATS), pp. 141-146, Dec. 2010.
  15. V. Tenentes, X. Kavousianos and E. Kalligeros, “Shrinking the Application Time of Test Set Embedding by Using Variable-State Skip LFSRs”, IEEE European Test Symposium(ETS), Inf. Digest., May 2008.
  16. V. Tenentes, X. Kavousianos and E. Kalligeros “State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores”, IEEE/ACM Design, Automation & Test in Europe (DATE) Conference, pp. 474-479, March 2008.
  17. Y. Sfikas, Y. Tsiatouhas “Physical Design Oriented DRAM Neighborhood Pattern Sensitive Fault Testing”, IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 108-113, 2009. (best paper award nominee)
  18. Y. Sfikas, Y. Tsiatouhas, M. Taouil and S. Hamdioui, “On Resistive Open Detection in DRAMs: The Charge Accumulation Effect”, IEEE European Test Symposium (ETS), May 2015.
  19. Y. Sfikas and Y. Tsiatouhas, “NLTF Based BIST Circuit for DRAM Testing,” 5th Int. Conference on Modern Circuits and Systems Technologies (MOCAST), May 2016.
  20. Y. Sfikas and Y. Tsiatouhas, “BTI and HCI Degradation Detection in SRAM Cells,” 6th International Conf. on Modern Circuits and Systems Technologies (MOCAST) , May 2017.
  21. Y. Sfikas and Y. Tsiatouhas, “Variation Tolerant BTI Monitoring in SRAM Cells,” IEEE Symposiun on On-Line Testing and Robust System Design (IOLTS), July 2017.
  22. Helen-Maria Dounavi, Yiorgos Sfikas and Yiorgos Tsiatouhas, “Aging Monitoring in SRAM Sense Amplifiers,” 7th Int. Conference on Modern Circuits and Systems Technologies (MOCAST), May
  23. Helen-Maria Dounavi, Yiorgos Sfikas and Yiorgos Tsiatouhas, “Periodic Aging Monitoring in SRAM Sense Amplifiers,” IEEE Symposiun on On-Line Testing and Robust System Design (IOLTS), July 2018.
  24. M. E. Plissiti, C. Papaioannou, Y. Sfikas, G. Papatheodorou, S.-I. Poulis, A. Efthymiou, Y. Tsiatouhas, “An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems,” Accepted for Presentation, IEEE International Mediterranean Conference on Communications and Networking (MeditCom), Sept 2021.

Workshops

  1. V. Tenentes and A. Papanikolaou “Interactive field-directed floorplan prototyping for 2D/3D IC’s ”, D43D: 4th Design for 3D Silicon Integration Workshop, June 25th-27th 2012, Lausanne.

PhD Dissertation

V. Tenentes, Embedded Testing Architectures. PhD dissertation