Research

VCAS Research Profile

VCAS Lab is dedicated to advancing research areas related to the design and testing of nanometer technology integrated circuits (digital, analog or mixed-signal) and systems as well as exploring novel system architectures of emerging device technologies and applications. Its mission aims at the continuous pursuit of research excellence through active participation in competitive National, European, and International research programs.

The Laboratory places strong emphasis on emerging technologies and cutting-edge research areas such as:

  • Circuits and systems to support Artificial Intelligence (AI)
  • Processing-in memory systems
  • Quantum computing
  • Testing, reliability and security of integrated systems
  • Low-power integrated systems
  • Advanced computer architecture
  • Optoelectronics

The Laboratory actively seeks funding opportunities by submitting proposals to relevant national and international calls, ensuring it remains at the forefront of technological innovation. Its work supports both fundamental research and real-world applications in AI, microelectronics, and next-generation computing systems.

University of Ioannina Rankings

The University of Ioannina is consistently ranked among the top universities in Greece and has a notable global presence, particularly in the fields of education and research. In the Center for World University Rankings (CWUR) 2024, it is ranked 774th globally out of 20,966 universities and is in the top 3.7% worldwide. Nationally, it’s ranked 4th among Greek universities.

  • Global Rankings CWUR (2024): 774th globally (Top 3.7% in the world)
  • National Rankings (Greece) CWUR (2024): 4th nationally
  • Regional Rankings CWUR (2024): 300th in Europe

The department of Computer Science and Engineering of the University of Ioannina is generally ranked well within Greece and internationally. Research.com lists the Computer Science and Engineering department as the second-best (2nd) university department in Greece for computer science, based on a total D-index of 427. In the Times Higher Education Subject Rankings 2024, it is ranked 801-1000th globally for computer science. Additionally, of the School of Engineering is ranked 4th among the top Greek university departments.

Academic/Industrial Partners of VCAS Lab members

Adveos University of Alabama Aristotle University of Thessaloniki ARM Bizzcom s.r.o. Brno University of Technology
University of Calgary Carnegie Mellon University Circuits Integrated Hellas Delft University of Technology Dogus University Duke University
Hellenic Open University University of Hertfordshire Integrated Systems Development S.A. University of Iowa University of Kashmir King Abdullah University of Science and Technology
University of Liverpool University of Manchester National and Kapodistrian University of Athens University of Peloponnese University of Patras Università di Pisa
University of Piraeus Politecnico di Torino University of Sharjah Sorbonne Université University of Southampton Southern Illinois University Carbondale
STMicroelectronics University of the Aegean Texas Instruments University of West Attica

Past research projects involving members of the lab (reverse chronological order):

    • BM-MAP (source: Bizzcom s.r.o.): Behavioural modelling and AI application mapping on memristor arrays. PhD scholarships provided by Bizzcom s.r.o., Slovakia for behavioural modelling of memristor devices and AI applications mapping on memristor crossbar arrays.
    • EPI (source: Horizon): The European Processor Initiative (EPI) is an EU Horizon funded project that aims to design and develop energy-efficient, high-performance RISC-V processors for exascale computing, targeting applications in AI, big data, automotive, and scientific simulations. Coordinated by the Barcelona Supercomputing Center, it involves partners like ARM and STMicroelectronics, and the University of Pisa, among others. During his sabbatical at the University of Pisa in Italy, in 2024, Dr. Tenentes contributed to the areas of fault-tolerant and secure processor architectures, by developing a RAS architecture and a resilience evaluation flow of post-quantum cryptographic accelerators against Deep Learning based side-channel attacks.
    • ARTEMIS – 2021-2023 (source: NSF and ESF): The Artemis project develops secure supply chain tracking through integrated hardware and software solutions, addressing issues like device spoofing and data integrity in IoT environments. The project focuses on evaluating the traceability capabilities on different supply chain networks and, then, proposing distributed as well as embedded system architectures for securing the traceability of supply chain products and assets. From an AI perspective, it employs intelligent risk analysis, adaptive security protocols, and machine learning-driven authentication to optimize blockchain-based attestation and ensure robust traceability, particularly for applications like the food supply chain. The project involves three Academic institutions (the University of Ioannina, the University of Piraeus and the University of Thessaly) and two companies. The first company, itrack (https://www.itrack.gr), develops systems for tracking supply chain logistics. The second company, the Floridis AEVEK, is the main supplier for the cold supply chain products at the largest supermarket chains that are active in Greece, such as Carrefur, AB Vasilopoulos, Lidl, Makro, Metro, and the Olympic Catering, to name a few; the company manages a huge fleet of chiller lorries and storage units for the cold supply chain. The Project is co‐financed by the European Regional Development Fund of the European Union and Greek national funds through the Operational Program Competitiveness, Entrepreneurship and Innovation, under the call RESEARCH – CREATE – INNOVATE (project code:Τ2EDK-02836. Grant: 996,650 €.
    • VIOLIN – 2018-2022 (source: NSF and ESF): The Violin project utilizes Visible Light Communication (VLC) for high-speed indoor connectivity in high-demand settings like airports and supply chains. Its AI component focuses on intelligent systems for adaptive modulation and interference management to enhance VLC network efficiency and user experience.
    • UniServer (source: ESF): The UniServer project, an EU Horizon 2020-funded initiative (2016–2019), aimed to develop a universal micro-server architecture for energy-efficient, high-performance, and secure edge computing. Coordinated by Queen’s University Belfast, it involved partners like ARM, IBM, and the University of Ioannina, where Dr. Vasileios Tenentes contributed as an ARM Research engineer. His work focused on runtime adaptation for power-noise management in micro-servers, developing on-chip power integrity characterization paradigms (hardware and software) to enhance energy efficiency and reliability. From an AI perspective, Dr Tenentes’ integrated machine learning-based models into runtime frameworks for adaptive fault tolerance, power optimization and resilience against power noise viruses, supporting IoT and edge applications.
    • PRiME: Power-efficient, Reliable, Many-core Embedded systems (source: EPSRC): The PRiME project, a £5.6m EPSRC-funded initiative (2013–2018) led by the University of Southampton, focused on developing power-efficient and reliable many-core embedded systems. It involved four UK universities (Southampton, Imperial College London, Manchester, Newcastle) and five companies, addressing energy consumption and reliability challenges in high-performance multicore processors. Dr Vasileios Tenentes contributed to fault-tolerant design and testing methodologies. The AI scope of this project included learning-based runtime algorithms for energy optimization, an AI-based runtime for improved resilience against power DoS attacks, and cross-layer frameworks to enhance system reliability.
    • RHEA: Resilient Hardware for Energy-efficient Applications (source: EPSRC): Dr Tenentes is a member of the RHEA team that has collaborated on resilient hardware for energy-efficient applications, which has been funded by EPSRC as the Resilient-Project. The RHEA project 2014-2017, was a three-year EPSRC-funded initiative, develops resilient and testable energy-efficient digital hardware for low-power devices. Its AI scope involves creating intelligent fault models and online monitoring systems to enhance reliability and testability of power management circuits, addressing challenges like BTI aging and soft errors through adaptive methods.
      The Resilient-Project outcomes have already been cited by a numerous prestigious publications in IEEE Conferences & Transactions, and the prestigious IEEE Spectrum Magazine.Our research was validated using chips provided by ARM Ltd, which was one of our industrial patterns.
    • REIN – Thallis (source: NSF and ESF): The REIN – Thallis project focused on advancing reliable and efficient integrated circuit design, emphasizing fault-tolerant techniques and testing methodologies for nanoscale technologies. It involved multiple Greek institutions, including the University of Ioannina VCAS research group led by Dr Yiorgos Tsiatouhas. The project explored timing error tolerance, soft error mitigation, and low-power testing for System-on-Chip (SoC) applications, leveraging AI-driven optimization for enhanced circuit reliability and performance
  • Heracletus II (source: NSF and ESF)
  • Pythagoras (source: NSF and ESF)

 

Journals

  1. J. Nako, G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Approximation of complex coefficient filters,” AEU – International Journal of Electronics and Communications, vol. 197, Dec. 2025, doi: 10.1016/j.aeue.2025.155800.
  2. V. Malamas, P. Kotzanikolaou, K. Nomikos, C. Zonios, V. Tenentes, and M. Psarakis, “HA-CAAP: Hardware-Assisted Continuous Authentication and Attestation Protocol for IoT Based on Blockchain,” IEEE Internet of Things Journal, vol. 12, no. 17, pp. 30537–30551, Sep. 2025, doi: 10.1109/JIOT.2025.3530775.
  3. J. Nako, G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Approximation of First–Order Complex Resonators in the Frequency–Domain,” IEEE Access, vol. 13, pp. 54494–54503, Apr. 2025, doi: 10.1109/ACCESS.2025.3553629.
  4. I. Rizos, G. Papatheodorou, and A. Efthymiou, “Designing Approximate Reduced Complexity Wallace Multipliers,” Electronics (Switzerland), vol. 14, no. 2, Jan. 2025, doi: 10.3390/electronics14020333.
  5. E. Paparsenos and Y. Tsiatouhas, “Radiation-hardened latch design with triple-node-upset recoverability,” AEU – International Journal of Electronics and Communications, vol. 187, Nov. 2024, doi: 10.1016/j.aeue.2024.155539.
  6. J. Nako, G. Tsirimokou, C. Psychalinos, A. S. Elwakil, B. J. Maundy, and P. Bertsias, “Reduced Complexity Approximation and Design of Gaussian Impulse Response Filters and Wavelets,” IEEE Access, vol. 12, pp. 160064–160073, Nov. 2024, doi: 10.1109/ACCESS.2024.3486776.
  7. J. Nako, G. Tsirimokou, C. Psychalinos, and S. Minaei, “Multi-phase sinusoidal oscillator design based on first-order shadow filters,” AEU – International Journal of Electronics and Communications, vol. 178, May 2024, doi: 10.1016/j.aeue.2024.155263.
  8. A. Koutra and V. Tenentes, “Multi-Vt-Based Energy Efficiency Optimization for ASIC Designs of the Double Secure Hash Algorithm Toward a Sustainable Bitcoin Network,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 3, pp. 1596–1600, Mar. 2024, doi: 10.1109/TCSII.2024.3350035.
  9. H.-M. Dounavi and Y. Tsiatouhas, “An aging monitoring scheme for SRAM decoders,” Integration, vol. 88, pp. 108–115, Jan. 2023, doi: 10.1016/j.vlsi.2022.09.009.
  10. S.-I. Poulis et al., “Effective Current Pre-Amplifiers for Visible Light Communication (VLC) Receivers,” Technologies, vol. 10, no. 1, Jan. 2022, doi: 10.3390/technologies10010036.
  11. G. Tsirimokou, S. Kapoulea, C. Psychalinos, and A. S. Elwakil, “Approximation and realization of power-law all-pass filters,” AEU – International Journal of Electronics and Communications, vol. 155, Oct. 2022, doi: 10.1016/j.aeue.2022.154341.
  12. D. Rossi and V. Tenentes, “Run-Time Thermal Management for Lifetime Optimization in Low-Power Designs,” Electronics (Switzerland), vol. 11, no. 3, Feb. 2022, doi: 10.3390/electronics11030411.
  13. V. Gerakis, Y. Tsiatouhas, and A. Hatzopoulos, “A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 37, no. 2, pp. 191–203, Apr. 2021, doi: 10.1007/s10836-021-05939-z.
  14. H.-M. Dounavi, Y. Sfikas, and Y. Tsiatouhas, “Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 37, no. 1, pp. 65–82, Feb. 2021, doi: 10.1007/s10836-021-05932-6.
  15. S. Kapoulea, G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Generalized Fully Adjustable Structure for Emulating Fractional-Order Capacitors and Inductors of Orders less than Two,” Circuits, Systems, and Signal Processing, vol. 39, no. 4, pp. 1797–1814, Apr. 2020, doi: 10.1007/s00034-019-01252-5.
  16. V. Tenentes, S. Das, D. Rossi, and B. M. Al-Hashimi, “Run-Time Protection of Multi-Core Processors from Power-Noise Denial-of-Service Attacks,” IEEE Transactions on Device and Materials Reliability, vol. 20, no. 2, pp. 319–328, Jun. 2020, doi: 10.1109/TDMR.2020.2994272.
  17. S. Kapoulea, G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Employment of the Padé approximation for implementing fractional-order lead/lag compensators,” AEU – International Journal of Electronics and Communications, vol. 120, Jun. 2020, doi: 10.1016/j.aeue.2020.153203.
  18. O. Domansky, R. Sotner, L. Langhammer, J. Jerabek, C. Psychalinos, and G. Tsirimokou, “Practical Design of RC Approximants of Constant Phase Elements and Their Implementation in Fractional-Order PID Regulators Using CMOS Voltage Differencing Current Conveyors,” Circuits, Systems, and Signal Processing, vol. 38, no. 4, pp. 1520–1546, Apr. 2019, doi: 10.1007/s00034-018-0944-z.
  19. H.-M. Dounavi, Y. Sfikas, and Y. Tsiatouhas, “Periodic monitoring of BTI induced aging in SRAM sense amplifiers,” IEEE Transactions on Device and Materials Reliability, vol. 19, no. 1, pp. 64–72, Mar. 2019, doi: 10.1109/TDMR.2019.2898862.
  20. P. Georgiou, F. Vartziotis, X. Kavousianos, and K. Chakrabarty, “Testing 3D-SoCs using 2-D time-division multiplexing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 12, pp. 3177–3185, Dec. 2018, doi: 10.1109/TCAD.2017.2780054.
  21. D. Rossi, V. Tenentes, S. M. Reddy, B. M. Al-Hashimi, and A. Brown, “Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 7, pp. 1345–1357, Jul. 2018, doi: 10.1109/TCAD.2017.2729399.
  22. C. Vastarouchas, G. Tsirimokou, and C. Psychalinos, “Extraction of Cole-Cole model parameters through low-frequency measurements,” AEU – International Journal of Electronics and Communications, vol. 84, pp. 355–359, Feb. 2018, doi: 10.1016/j.aeue.2017.11.020.
  23. G. Tsirimokou, C. Psychalinos, A. S. Elwakil, and K. N. Salama, “Electronically Tunable Fully Integrated Fractional-Order Resonator,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 2, pp. 166–170, Feb. 2018, doi: 10.1109/TCSII.2017.2684710.
  24. G. Tsirimokou, A. Kartci, J. Koton, N. Herencsar, and C. Psychalinos, “Comparative Study of Discrete Component Realizations of Fractional-Order Capacitor and Inductor Active Emulators,” Journal of Circuits, Systems and Computers, vol. 27, no. 11, Sep. 2018, doi: 10.1142/S0218126618501700.
  25. V. Tenentes, D. Rossi, S. Khursheed, B. M. Al-Hashimi, and K. Chakrabarty, “Leakage current analysis for diagnosis of bridge defects in power-gating designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 4, pp. 883–895, Apr. 2018, doi: 10.1109/TCAD.2017.2729462.
  26. F. Vartziotis, X. Kavousianos, P. Georgiou, and K. Chakrabarty, “A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-V-dd SoCs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 11, pp. 1911–1924, Nov. 2017, doi: 10.1109/TCAD.2017.2664062.
  27. G. Tsirimokou, “A systematic procedure for deriving RC networks of fractional-order elements emulators using MATLAB,” AEU – International Journal of Electronics and Communications, vol. 78, pp. 7–14, Aug. 2017, doi: 10.1016/j.aeue.2017.05.003.
  28. I. Dimeas, G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Experimental Verification of Fractional-Order Filters Using a Reconfigurable Fractional-Order Impedance Emulator,” Journal of Circuits, Systems and Computers, vol. 26, no. 9, Sep. 2017, doi: 10.1142/S0218126617501420.
  29. C. Vastarouchas, G. Tsirimokou, T. J. Freeborn, and C. Psychalinos, “Emulation of an electrical-analogue of a fractional-order human respiratory mechanical impedance model using OTA topologies,” AEU – International Journal of Electronics and Communications, vol. 78, pp. 201–208, Aug. 2017, doi: 10.1016/j.aeue.2017.03.021.
  30. G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Fractional-order electronically controlled generalized filters,” International Journal of Circuit Theory and Applications, vol. 45, no. 5, pp. 595–612, May 2017, doi: 10.1002/cta.2250.
  31. M. D. Gutierrez, V. Tenentes, D. Rossi, and T. J. Kazmierski, “Susceptible Workload Evaluation and Protection using Selective Fault Tolerance,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 33, no. 4, pp. 463–477, Aug. 2017, doi: 10.1007/s10836-017-5668-7.
  32. G. Tsirimokou, C. Psychalinos, A. S. Elwakil, and K. N. Salama, “Experimental behavior evaluation of series and parallel connected constant phase elements,” AEU – International Journal of Electronics and Communications, vol. 74, pp. 5–12, Apr. 2017, doi: 10.1016/j.aeue.2017.01.010.
  33. R. Sotner, J. Jerabek, J. Petrzela, O. Domansky, G. Tsirimokou, and C. Psychalinos, “Synthesis and design of constant phase elements based on the multiplication of electronically controllable bilinear immittances in practice,” AEU – International Journal of Electronics and Communications, vol. 78, pp. 98–113, Aug. 2017, doi: 10.1016/j.aeue.2017.05.013.
  34. V. Tenentes, D. Rossi, S. Yang, S. Khursheed, B. M. Al-Hashimi, and S. R. Gunn, “Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1397–1407, Apr. 2017, doi: 10.1109/TVLSI.2016.2626218.
  35. D. Rossi, V. Tenentes, S. Yang, S. Khursheed, and B. M. Al-Hashimi, “Aging Benefits in Nanometer CMOS Designs,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 3, pp. 324–328, Mar. 2017, doi: 10.1109/TCSII.2016.2561206.
  36. J. Liaperdos, A. Arapoyanni, and Y. Tsiatouhas, “State reduction for efficient digital calibration of analog/RF integrated circuits,” Analog Integrated Circuits and Signal Processing, vol. 90, no. 1, pp. 65–79, Jan. 2017, doi: 10.1007/s10470-016-0880-4.
  37. B. Halak, V. Tenentes, and D. Rossi, “The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology,” Microelectronics Reliability, vol. 67, pp. 74–81, Dec. 2016, doi: 10.1016/j.microrel.2016.10.018.
  38. D. Rossi, V. Tenentes, S. Yang, S. Khursheed, and B. M. Al-Hashimi, “Reliable Power Gating with NBTI Aging Benefits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 8, pp. 2735–2744, Aug. 2016, doi: 10.1109/TVLSI.2016.2519385.
  39. S. Valadimas, Y. Tsiatouhas, and A. Arapoyanni, “Timing error tolerance in small core designs for SoC applications,” IEEE Transactions on Computers, vol. 65, no. 2, pp. 654–663, Feb. 2016, doi: 10.1109/TC.2015.2420562.
  40. Y. Sfikas and Y. Tsiatouhas, “Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs,” IEEE Transactions on Computers, vol. 65, no. 7, pp. 2339–2345, Jul. 2016, doi: 10.1109/TC.2015.2479606.
  41. G. Tsirimokou and C. Psychalinos, “Ultra-low voltage fractional-order circuits using current mirrors,” International Journal of Circuit Theory and Applications, vol. 44, no. 1, pp. 109–126, Jan. 2016, doi: 10.1002/cta.2066.
  42. C. Psychalinos, G. Tsirimokou, and A. S. Elwakil, “Switched-Capacitor Fractional-Step Butterworth Filter Design,” Circuits, Systems, and Signal Processing, vol. 35, no. 4, pp. 1377–1393, Apr. 2016, doi: 10.1007/s00034-015-0110-9.
  43. F. Khateb, D. Kubánek, G. Tsirimokou, and C. Psychalinos, “Fractional-order filters based on low-voltage DDCCs,” Microelectronics Journal, vol. 50, pp. 50–59, Apr. 2016, doi: 10.1016/j.mejo.2016.02.002.
  44. D. Kubánek, F. Khateb, G. Tsirimokou, and C. Psychalinos, “Practical Design and Evaluation of Fractional-Order Oscillator Using Differential Voltage Current Conveyors,” Circuits, Systems, and Signal Processing, vol. 35, no. 6, pp. 2003–2016, Jun. 2016, doi: 10.1007/s00034-016-0243-5.
  45. G. Tsirimokou, C. Psychalinos, T. J. Freeborn, and A. S. Elwakil, “Emulation of current excited fractional-order capacitors and inductors using OTA topologies,” Microelectronics Journal, vol. 55, pp. 70–81, Sep. 2016, doi: 10.1016/j.mejo.2016.06.008.
  46. G. Tsirimokou, S. Koumousi, and C. Psychalinos, “Design of fractional-order filters using Current Feedback Operational Amplifiers,” Journal of Engineering Science and Technology Review, vol. 9, no. 4, pp. 77–81, Aug. 2016, doi: 10.25103/jestr.094.12.
  47. G. Tsirimokou, C. Psychalinos, A. S. Elwakil, and K. N. Salama, “Experimental verification of on-chip CMOS fractional-order capacitor emulators,” Electronics Letters, vol. 52, no. 15, pp. 1298–1300, Jul. 2016, doi: 10.1049/el.2016.1457.
  48. V. Tenentes, S. Khursheed, D. Rossi, S. Yang, and B. M. Al-Hashimi, “DFT Architecture with Power-Distribution-Network Consideration for Delay-Based Power Gating Test,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 12, pp. 2013–2024, Dec. 2015, doi: 10.1109/TCAD.2015.2446939.
  49. F. Vartziotis, X. Kavousianos, K. Chakrabarty, A. Jain, and R. Parekhji, “Time-Division Multiplexing for Testing DVFS-Based SoCs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 4, pp. 668–681, Apr. 2015, doi: 10.1109/TCAD.2015.2394462.
  50. S. Matakias, Y. Tsiatouhas, A. Arapoyanni, and T. Haniotakis, “A current monitoring technique for IDDQ testing in digital integrated circuits,” Integration, vol. 50, pp. 48–60, Jun. 2015, doi: 10.1016/j.vlsi.2015.01.005.
  51. G. Tsirimokou, C. Psychalinos, A. Allagui, and A. S. Elwakil, “Simple non-impedance-based measuring technique for supercapacitors,” Electronics Letters, vol. 51, no. 21, pp. 1699–1701, Oct. 2015, doi: 10.1049/el.2015.2395.
  52. G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Emulation of a constant phase element using operational transconductance amplifiers,” Analog Integrated Circuits and Signal Processing, vol. 85, no. 3, pp. 413–423, Dec. 2015, doi: 10.1007/s10470-015-0626-8.
  53. G. Tsirimokou, C. Psychalinos, F. A. Khanday, and N. A. Shah, “0.5 V sinh-domain differentiator,” International Journal of Electronics Letters, vol. 3, no. 1, pp. 34–44, Mar. 2015, doi: 10.1080/00207217.2014.901425.
  54. K. Katsarou and Y. Tsiatouhas, “Soft error interception latch: Double node charge sharing SEU tolerant design,” Electronics Letters, vol. 51, no. 4, pp. 330–332, Feb. 2015, doi: 10.1049/el.2014.4374.
  55. S. Valadimas, Y. Tsiatouhas, A. Arapoyanni, and X. Kavousianos, “The time dilation technique for timing error tolerance,” IEEE Transactions on Computers, vol. 63, no. 5, pp. 1277–1286, May 2014, doi: 10.1109/TC.2012.289.
  56. Z. Zhang, X. Kavousianos, K. Chakrabarty, and Y. Tsiatouhas, “Static power reduction using variation-tolerant and reconfigurable multi-mode power switches,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 1, pp. 13–26, Jan. 2014, doi: 10.1109/TVLSI.2012.2233505.
  57. G. Tsirimokou and C. Psychalinos, “Realization of current-mirror filters with large time-constants,” AEU – International Journal of Electronics and Communications, vol. 68, no. 12, pp. 1261–1264, Dec. 2014, doi: 10.1016/j.aeue.2014.07.007.
  58. Y. Sfikas, Y. E. Tsiatouhas, and S. Hamdioui, “Layout-based refined NPSF model for DRAM characterization and testing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 6, pp. 1446–1450, Jun. 2014, doi: 10.1109/TVLSI.2013.2266281.
  59. E. Arvaniti and Y. Tsiatouhas, “Low-power scan testing: A scan chain partitioning and scan hold based technique,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 30, no. 3, pp. 329–341, Jun. 2014, doi: 10.1007/s10836-014-5453-9.
  60. G. Tsirimokou and C. Psychalinos, “Ultra-low voltage fractional-order differentiator and integrator topologies: an application for handling noisy ECGs,” Analog Integrated Circuits and Signal Processing, vol. 81, no. 2, pp. 393–405, Nov. 2014, doi: 10.1007/s10470-014-0391-0.
  61. V. Tenentes, X. Kavousianos, and V. Tenentes, “High-quality statistical test compression with narrow ATE interface,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 9, pp. 1369–1382, Sep. 2013, doi: 10.1109/TCAD.2013.2256394.
  62. G. Tsirimokou, C. Laoudias, and C. Psychalinos, “0.5-V fractional-order companding filters,” International Journal of Circuit Theory and Applications, vol. 43, no. 9, pp. 1105–1126, Sep. 2015, doi: 10.1002/cta.1995.
  63. S. Valadimas, Y. Tsiatouhas, A. Arapoyanni, and P. Xarchakos, “Effective timing error tolerance in flip-flop based core designs,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 29, no. 6, pp. 795–804, Dec. 2013, doi: 10.1007/s10836-013-5419-3.
  64. J. Liaperdos, A. Arapoyanni, and Y. Tsiatouhas, “Adjustable RF mixers alternate test efficiency optimization by the reduction of test observables,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 9, pp. 1383–1394, Sep. 2013, doi: 10.1109/TCAD.2013.2255128.
  65. J. Liaperdos, A. Arapoyanni, and Y. Tsiatouhas, “A built-in voltage measurement technique for the calibration of RF mixers,” IEEE Transactions on Instrumentation and Measurement, vol. 62, no. 4, pp. 732–742, Apr. 2013, doi: 10.1109/TIM.2013.2246903.
  66. C. Efstathiou, Z. Owda, and Y. Tsiatouhas, “New high-speed multioutput carry look-ahead adders,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 10, pp. 667–671, Oct. 2013, doi: 10.1109/TCSII.2013.2278088.
  67. G. Tsirimokou, C. Laoudias, and C. Psychalinos, “Tinnitus detector realization using sinh-domain circuits,” Journal of Low Power Electronics, vol. 9, no. 4, pp. 458–470, Dec. 2013, doi: 10.1166/jolpe.2013.1272.
  68. X. Kavousianos, K. Chakrabarty, A. Jain, and R. Parekhji, “Test schedule optimization for multicore SoCs: Handling dynamic voltage scaling and multiple voltage islands,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 11, pp. 1754–1766, Nov. 2012, doi: 10.1109/TCAD.2012.2203600.
  69. X. Kavousianos, V. Tenentes, K. Chakrabarty, and E. Kalligeros, “Defect-oriented LFSR reseeding to target unmodeled defects using stuck-at test sets,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 12, pp. 2330–2335, Dec. 2011, doi: 10.1109/TVLSI.2010.2079961.
  70. V. Tenentes and X. Kavousianos, “Self-freeze linear decompressors: Test pattern generators for low power scan testing,” Lecture Notes in Electrical Engineering, vol. 105 LNEE, pp. 217–230, Jan. 2011, doi: 10.1007/978-94-007-1488-5_13.
  71. X. Kavousianos and K. Chakrabarty, “Generation of compact stuck-at test sets targeting unmodeled defects,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 5, pp. 787–791, May 2011, doi: 10.1109/TCAD.2010.2101750.
  72. A. Floros, Y. Tsiatouhas, and X. Kavousianos, “Timing error detection and correction by time dilation,” IFIP Advances in Information and Communication Technology, vol. 313, pp. 271–285, Jan. 2010, doi: 10.1007/978-3-642-12267-5_15.
  73. V. Tenentes, X. Kavousianos, and E. Kalligeros, “Single and variable-state-skip LFSRs: Bridging the gap between test data compression and test set embedding for IP cores,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 10, pp. 1640–1644, Oct. 2010, doi: 10.1109/TCAD.2010.2051096.
  74. L. E. Dermentzoglou, A. Arapoyanni, and Y. Tsiatouhas, “A built-in-test circuit for RF differential low noise amplifiers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 7, pp. 1549–1558, Jul. 2010, doi: 10.1109/TCSI.2009.2035417.
  75. A. Efthymiou, “Initialization-based test pattern generation for asynchronous circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 4, pp. 591–601, Apr. 2010, doi: 10.1109/TVLSI.2009.2013470.
  76. X. Kavousianos, D. Bakalis, and D. Nikolos, “Efficient partial scan cell gating for low-power scan-based testing,” ACM Transactions on Design Automation of Electronic Systems, vol. 14, no. 2, Mar. 2009, doi: 10.1145/1497561.1497571.
  77. I. Fudos, X. Kavousianos, D. Markouzis, and Y. Tsiatouhas, “Placement and routing in computer aided design of standard cell arrays by exploiting the structure of the interconnection graph,” Computer-Aided Design and Applications, vol. 5, no. 1–4, pp. 325–337, Jan. 2008, doi: 10.3722/cadaps.2008.325-337.
  78. S. Matakias, Y. Tsiatouhas, T. Haniotakis, and A. Arapoyanni, “A current mode, parallel, two-rail code checker,” IEEE Transactions on Computers, vol. 57, no. 8, pp. 1032–1045, Aug. 2008, doi: 10.1109/TC.2008.59.
  79. X. Kavousianos, E. Kalligeros, and D. Nikolos, “Multilevel-Huffman test-data compression for IP cores with multiple scan chains,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 7, pp. 926–931, Jul. 2008, doi: 10.1109/TVLSI.2008.2000448.
  80. X. Kavousianos, E. Kalligeros, and D. Nikolos, “Test data compression based on variable-to-variable huffman encoding with codeword reusability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 7, pp. 1333–1338, Jul. 2008, doi: 10.1109/TCAD.2008.923100.
  81. T. Haniotakis, Y. Tsiatouhas, D. Nikolos, and C. Efstathiou, “Testable designs of multiple precharged Domino circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 4, pp. 461–465, Apr. 2007, doi: 10.1109/TVLSI.2007.893664.
  82. Y. E. Tsiatouhas, “A stress-relaxed negative voltage-level converter,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 3, pp. 282–286, Mar. 2007, doi: 10.1109/TCSII.2006.886877.
  83. X. Kavousianos, E. Kalligeros, and D. Nikolos, “Multilevel Huffman coding: An efficient test-data compression method for IP cores,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 6, pp. 1070–1083, Jun. 2007, doi: 10.1109/TCAD.2006.885830.
  84. X. Kavousianos, E. Kalligeros, and D. Nikolos, “Optimal selective Huffman coding for test-data compression,” IEEE Transactions on Computers, vol. 56, no. 8, pp. 1146–1152, Aug. 2007, doi: 10.1109/TC.2007.1057.
  85. K. Limniotis, Y. Tsiatouhas, T. Haniotakis, and A. Arapoyanni, “A design technique for energy reduction in NORA CMOS logic,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 12, pp. 2647–2655, Dec. 2006, doi: 10.1109/TCSI.2006.885690.
  86. A. Efthymiou, J. Bainbridge, and D. Edwards, “Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 12, pp. 1384–1393, Dec. 2005, doi: 10.1109/TVLSI.2005.862722.
  87. L. Dermentzoglou, Y. Tsiatouhas, and A. A. Arapoyanni, “A design for testability technique for mixed-signal differential circuits,” in Journal of Physics: Conference Series, vol. 10, pp. 348–351, Jan. 2005, doi: 10.1088/1742-6596/10/1/085.
  88. E. Kalligeros, X. Kavousianos, and D. Nikolos, “Multiphase BIST,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 10, pp. 1429–1446, Oct. 2004, doi: 10.1109/TCAD.2004.833617.
  89. L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A design for testability scheme for CMOS LC-tank voltage controlled oscillators,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 20, no. 2, pp. 133–142, Apr. 2004, doi: 10.1023/B:JETT.0000023677.58861.81.
  90. Th. Haniotakis, Y. Tsiatouhas, C. Efstathiou, and D. Nikolos, “Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers,” International Journal of Electronics, vol. 90, no. 2, pp. 145–158, Feb. 2003, doi: 10.1080/00207210310001595383.
  91. A. Chrisanthopoulos, Y. Moisiadis, Y. Tsiatouhas, and A. Arapoyanni, “Comparative study of different current mode sense amplifiers in submicron CMOS technology,” IEE Proceedings: Circuits, Devices and Systems, vol. 149, no. 3, pp. 154–158, Jun. 2002, doi: 10.1049/ip-cds:20020425.
  92. X. Kavousianos, D. Bakalis, D. Nikolos, and S. Tragoudas, “A new built-in TPG method for circuits with random pattern resistant faults,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 859–866, Jul. 2002, doi: 10.1109/TCAD.2002.1013898.
  93. S. B. Furber, A. Efthymiou, J. D. Garside, D. W. Lloyd, M. J. G. Lewis, and S. Temple, “Power management in the amulet microprocessors,” IEEE Design and Test of Computers, vol. 18, no. 2, pp. 42–51, Mar. 2001, doi: 10.1109/54.914617.
  94. G. Kamoulakos, Th. Haniotakis, Y. Tsiatouhas, J.-P. Schoellkopf, and A. Arapoyanni, “Device simulation of a n-DMOS cell with trench isolation,” Microelectronics Journal, vol. 32, no. 1, pp. 75–80, Jan. 2001, doi: 10.1016/S0026-2692(00)00108-7.
  95. G. Kamoulakos, Y. Tsiatouhas, A. Chrisanthopoulos, and A. Arapoyanni, “A high-density DRAM cell with built-in gain stage,” IEEE Transactions on Electron Devices, vol. 48, no. 6, pp. 1194–1199, Jun. 2001, doi: 10.1109/16.925247.
  96. D. Bakalis, X. Kavousianos, H. T. Vergos, D. Nikolos, and G. Ph. Alexiou, “Low power built-in self-test schemes for array and booth multipliers,” VLSI Design, vol. 12, no. 3, pp. 431–448, Jan. 2001, doi: 10.1155/2001/67893.
  97. H. T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, and M. Nicolaidis, “Path delay fault testing of multiplexer-based shifters,” International Journal of Electronics, vol. 88, no. 8, pp. 923–937, Aug. 2001, doi: 10.1080/00207210110058139.
  98. G. Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, and A. Arapoyanni, “Management of charge pump circuits,” Integration, the VLSI Journal, vol. 30, no. 1, pp. 91–101, Oct. 2000, doi: 10.1016/S0167-9260(00)00012-2.
  99. X. Kavousianos, D. Nikolos, and G. Sidiropoulos, “Novel single and double output TSC CMOS checkers for m-out-of-n codes,” VLSI Design, vol. 11, no. 1, pp. 35–45, Jan. 2000, doi: 10.1155/2000/89292.
  100. A. Chrisanthopoulos, Y. Moisiadis, Y. Tsiatouhas, and G. Kamoulakos, “Current mode sense amplifiers design in 0.25um CMOS technology,” pp. 66–70, Jan. 2000. [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-4944244997&partnerID=40&md5=7d51c3d09b2acf1952b4d0f1c4879ba7.
  101. Y. Tsiatouhas, A. Chrisanthopoulos, Th. Haniotakis, and G. Kamoulakos, “A new sense amplifier for submicron CMOS technology memories,” pp. 90–93, Jan. 2000. [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-4944261439&partnerID=40&md5=de7fc55fbdd1d9a0139d226c914fbc26.
  102. Y. Moisiadis, I. Bouras, A. Efthymiou, and C. Papadas, “Fast 1V bootstrapped inverter suitable for standard CMOS technologies,” Electronics Letters, vol. 35, no. 2, pp. 109–111, Jan. 1999, doi: 10.1049/el:19990092.
  103. X. Kavousianos, D. Nikolos, G. Foukarakis, and T. Gnardellis, “New efficient totally self-checking Berger code checkers,” Integration, the VLSI Journal, vol. 28, no. 1, pp. 101–118, Sep. 1999, doi: 10.1016/S0167-9260(99)00013-9.
  104. X. Kavousianos and D. Nikolos, “Modular TSC checkers for Bose-Lin and Bose codes,” in Proceedings of the IEEE VLSI Test Symposium, pp. 354–360, Apr. 1999. [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-0032661186&partnerID=40&md5=f4d8d2a3852084cd4edc2631dcd079dd.
  105. Y. Tsiatouhas, T. Haniotakis, D. Nikolos, A. Paschalis, and C. Halatsis, “Hierarchical robust test generation for CMOS circuit stuck-open faults,” International Journal of Electronics, vol. 82, no. 1, pp. 45–60, Jan. 1997, doi: 10.1080/002072197136264.
  106. Y. Tsiatouhas, Th. Haniotakis, C. Halatsis, and A. Arapoyanni, “Design of stuck-open fault testable CMOS complex gates,” Electronics Letters, vol. 32, no. 4, pp. 315–317, Feb. 1996, doi: 10.1049/el:19960247.
  107. Y. Tsiatouhas, A. Paschalis, D. Nikolos, and C. Halatsis, “Robust test generation for transistor stuck-open faults in CMOS complex gates,” International Journal of Electronics, vol. 79, no. 2, pp. 129–142, Aug. 1995, doi: 10.1080/00207219508926255.

Book Chapters

  1. H-M. Dounavi, S. Sfikas and Y. Tsiatouhas, “Aging Monitors for SRAM Memory Cells and Sense Amplifiers,” Chapter in the Book: Ageing of Integrated Circuits: Causes, Effects and Mitigation Techniques, editor: Basel Halak, Springer, ISBN: 978-3-030-23780-6, 2020.
  2. J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “Machine Learning in Alternate Testing of Integrated Circuits,” Chapter in the Book: Machine Learning Paradigms: Applications of Learning and Analytics in Intelligent Systems, editors: George A. Tsihrintzis, Maria Virvou, Lakhmi C. Jain, Springer, ISBN: 978-3-030-15627-5, 2019.
  3. V. Tenentes and X. Kavousianos “Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing”, Chapter in the Book: Designing Very Large Scale Integration Systems: Emerging Trends & Challenges, editors: N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Springer, ISBN: -, 2011.
  4. A. Floros, Y. Tsiatouhas and X. Kavousianos, “Timing Error Detection and Correction by Time Dilation,” Chapter in the Book: VLSI-SoC: Design Methodologies for SoC and SiP, editors: C. Piguet, R. Reis, D. Soudris, Springer, ISBN: 978-3-642-12266-8, 2010.

Conferences

  1. D. Georgoulas, Y. Tsiatouhas and V. Tenentes, “CAS-PUF: Current-Mode Array-Type Strong PUF for Secure Computing in Area Constrained SoCs,”
    in 2025 Design, Automation & Test in Europe Conference (DATE), Lyon, France, pp. 1-7, doi: 10.1109/DATE64628.2025.10992979
  2. I. Rizos, G. Papatheodorou, and A. Efthymiou, “Exploring the Design Space of 32×32 Approximate Reduced Complexity Wallace Multipliers,” in 2024 13th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2024, doi: 10.1109/MOCAST61810.2024.10615792.
  3. J. Nako, G. Tsirimokou, and C. Psychalinos, “Minimum Active Component Count Formant and Inverse Formant Filters Designs,” in 2024 47th International Conference on Telecommunications and Signal Processing (TSP), 2024, pp. 183–186, doi: 10.1109/TSP63128.2024.10605942.
  4. J. Nako, G. Tsirimokou, and C. Psychalinos, “Reducing the Spread of Passive Elements Values in Power-Law Transfer Functions,” in 2024 47th International Conference on Telecommunications and Signal Processing (TSP), 2024, pp. 6–9, doi: 10.1109/TSP63128.2024.10605979.
  5. J. Nako, G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Design of Generalized Frequency Domain Exponential Filters,” in NILES 2024 – 6th Novel Intelligent and Leading Emerging Sciences Conference, Proceedings, 2024, pp. 93–96, doi: 10.1109/NILES63360.2024.10753191.
  6. G. Papatheodorou, I. Rizos, and A. Efthymiou, “Design Space Exploration of Partial Product Reduction Stage on 8×8 Approximate Multipliers,” in 2024 Panhellenic Conference on Electronics and Telecommunications (PACET), 2024, doi: 10.1109/PACET60398.2024.10497018.
  7. E. Paparsenos and Y. Tsiatouhas, “Triple-Node-Upset Recoverable Radiation-Hardened by Design Latch,” in 2024 Panhellenic Conference on Electronics and Telecommunications (PACET), 2024, doi: 10.1109/PACET60398.2024.10497044.
  8. M. E. Plissiti et al., “Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems,” in 6th International Conference on Artificial Intelligence in Information and Communication (ICAIIC), 2024, pp. 401–406, doi: 10.1109/ICAIIC60209.2024.10463371.
  9. S. Spyridonos and Y. Tsiatouhas, “Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change Memories,” in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, doi: 10.23919/date58400.2024.10546778.
  10. V. Tenentes, S. Di Matteo, C. Zonios, D. Rossi, and S. Saponara, “RTL Flow for the Power Side-Channel Resilience Assessment of a Post-quantum SHA-3 Accelerator,” in 2024 13th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2024, doi: 10.1109/MOCAST61810.2024.10615493.
  11. K. Tsampiras, A. Liontos, and V. Tenentes, “Evaluating Trusted Firmware Remote Attestation on ARM and RISC-V Edge Computing Prototypes,” in 2024 13th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2024, doi: 10.1109/MOCAST61810.2024.10615972.
  12. C. Dilopoulou and Y. Tsiatouhas, “BTI Aging Influence and Mitigation in Neural Networks Oriented In-Memory Computing SRAMs,” in 2023 12th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2023, doi: 10.1109/MOCAST57943.2023.10176426.
  13. J. Nako, S. Kapoulea, P. Bertsias, G. Tsirimokou, and C. Psychalinos, “Interdisciplinary Applications of Non-Integer Order Circuits & Systems,” in 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2023, doi: 10.1109/CNNA60945.2023.10652842.
  14. J. Nako, G. Tsirimokou, and C. Psychalinos, “Generalized Non-Integer Order Controllers Implementations,” in 2023 46th International Conference on Telecommunications and Signal Processing (TSP), 2023, pp. 134–138, doi: 10.1109/TSP59544.2023.10197819.
  15. J. Nako, G. Tsirimokou, and C. Psychalinos, “Simple Designs of Power-Law Basic and Inverse Filters,” in 5th Novel Intelligent and Leading Emerging Sciences Conference (NILES), 2023, pp. 175–178, doi: 10.1109/NILES59815.2023.10296652.
  16. D. Rossi, N. Canino, S. Di Matteo, S. Saponara, and V. Tenentes, “Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures,” in 2023 8th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), 2023, doi: 10.1109/SEEDA-CECNSM61561.2023.10470707.
  17. V. Tenentes et al., “Embedded Platforms for Trusted Edge Computing Towards Quality Assurance Along the Supply Chain,” in 2023 8th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), 2023, doi: 10.1109/SEEDA-CECNSM61561.2023.10470545.
  18. A. Koutra and V. Tenentes, “High Throughput and Energy Efficient SHA-2 ASIC Design for Continuous Integrity Checking Applications,” in 2023 IEEE European Test Symposium (ETS), 2023, doi: 10.1109/ETS56758.2023.10174095.
  19. A. Xynos, V. Tenentes, and Y. Tsiatouhas, “SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs,” in 2023 IEEE European Test Symposium (ETS), 2023, doi: 10.1109/ETS56758.2023.10173941.
  20. G. Megas, G. Papatheodorou, Y. Sfikas, A. Efthymiou, and Y. Tsiatouhas, “Experimental Evaluation of a Euclidean Distances based 3-Color Shift Keying Scheme for Visible Light Communications,” in 2022 Panhellenic Conference on Electronics and Telecommunications (PACET), 2022, doi: 10.1109/PACET56979.2022.9976367.
  21. C. Papaioannou et al., “Signal Decoding in an NLOS VLC System with the Presence of Anti-Reflective Obstacles,” in 2022 IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom), 2022, pp. 303–309, doi: 10.1109/BlackSeaCom54372.2022.9858232.
  22. S. Spyridonos and Y. Tsiatouhas, “BTI Aging Influence on Charge Pump Circuits,” in 2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2022, doi: 10.1109/MOCAST54814.2022.9837768.
  23. C. Zonios and V. Tenentes, “REVOLVER: A Zero-Step Execution Emulation Framework for Mitigating Power Side-Channel Attacks on ARM64,” in 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2022, doi: 10.1109/IOLTS56730.2022.9897425.
  24. C. Zonios and V. Tenentes, “Energy Efficient Speech Command Recognition for Private Smart Home IoT Applications,” in 2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2021, doi: 10.1109/MOCAST52088.2021.9493392.
  25. M. E. Plissiti et al., “An Efficient Adaptive Thresholding Scheme for Signal Decoding in NLOS VLC Systems,” in 2021 IEEE International Mediterranean Conference on Communications and Networking (MeditCom), 2021, pp. 378–382, doi: 10.1109/MeditCom49071.2021.9647560.
  26. V. Gerakis, Y. Tsiatouhas, and A. Hatzopoulos, “An Alternative Post-bond Testing Method for TSVs,” in 2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2020, doi: 10.1109/MOCAST49295.2020.9200295.
  27. H.-M. Dounavi and Y. Tsiatouhas, “Monitoring of BTI and HCI Aging in SRAM Decoders,” in 2020 IEEE European Test Symposium (ETS), 2020, doi: 10.1109/ETS48528.2020.9131565.
  28. P. Bertsias, G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Fully Electronically Tunable Inverse Fractional-Order Filter Designs,” in NILES 2019 – Novel Intelligent and Leading Emerging Sciences Conference, 2019, pp. 42–45, doi: 10.1109/NILES.2019.8909317.
  29. C. Efstathiou and Y. Tsiatouhas, “On the Static CMOS Implementation of Magnitude Comparators,” in 2019 IEEE 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019, pp. 103–106, doi: 10.1109/PATMOS.2019.8862135.
  30. P. Georgiou, I. Theodosopoulos, and X. Kavousianos, “K3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-Multiplexing,” in 2019 IEEE European Test Symposium (ETS), 2019, doi: 10.1109/ETS.2019.8791520.
  31. P. Georgiou, X. Kavousianos, R. Cantoro, and M. Sonza Reorda, “Fault-Independent Test-Generation for Software-Based Self-Testing,” IEEE Transactions on Device and Materials Reliability, vol. 19, no. 2, pp. 341–349, Jun. 2019, doi: 10.1109/TDMR.2019.2911022.
  32. S. Kapoulea, G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “OTA-C Implementation of Fractional-Order Lead/Lag Compensators,” in NILES 2019 – Novel Intelligent and Leading Emerging Sciences Conference, 2019, pp. 38–41, doi: 10.1109/NILES.2019.8909292.
  33. A. Najdi, D. Rossi, and V. Tenentes, “Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits,” in 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, pp. 281–286, doi: 10.1109/IOLTS.2019.8854403.
  34. V. Tenentes, S. Das, D. Rossi, and B. M. Al-Hashimi, “Run-time Detection and Mitigation of Power-Noise Viruses,” in 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, pp. 275–280, doi: 10.1109/IOLTS.2019.8854375.
  35. G. Vlachogiannakis et al., “A Self-Calibrated Fractional-N PLL for WiFi 6 / 802.11ax in 28nm FDSOI CMOS,” in ESSCIRC 2019 – IEEE 45th European Solid State Circuits Conference, 2019, pp. 105–108, doi: 10.1109/ESSCIRC.2019.8902919.
  36. C. Efstathiou, K. Dimolikas, C. Papaioannou, and Y. Tsiatouhas, “Low Power and High Speed Static CMOS Digital Magnitude Comparators,” in 2018 25th IEEE International Conference on Electronics Circuits and Systems (ICECS), 2018, pp. 249–252, doi: 10.1109/ICECS.2018.8617949.
  37. H.-M. Dounavi, Y. Sfikas, and Y. Tsiatouhas, “Aging Monitoring in SRAM Sense Amplifiers,” in 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2018, pp. 12–16, doi: 10.1109/IOLTS.2018.8474169.
  38. H.-M. Dounavi, Y. Sfikas, and Y. Tsiatouhas, “Aging Monitoring in SRAM Sense Amplifiers,” in 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2018, pp. 1–4, doi: 10.1109/MOCAST.2018.8376646.
  39. D. Rossi, V. Tenentes, S. Khursheed, and S. M. Reddy, “Recycled IC Detection Through Aging Sensor,” in 2018 IEEE European Test Symposium (ETS), 2018, pp. 1–2, doi: 10.1109/ETS.2018.8400713.
  40. V. Tenentes, S. Khursheed, B. M. Al-Hashimi, S. Zhong, and S. Yang, “High Quality Testing of Grid Style Power Gating,” in Proceedings of the Asian Test Symposium, 2018, pp. 186–191, doi: 10.1109/ATS.2014.37.
  41. P. Georgiou, X. Kavousianos, R. Cantoro, and M. S. Reorda, “Fault-Independent Test-Generation for Software-Based Self-Testing,” in 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2018, pp. 79–84, doi: 10.1109/IOLTS.2018.8474081.
  42. G. Tsirimokou, C. Psychalinos, A. Elwakil, and B. Maundy, “Fractional-Order Multiphase Sinusoidal Oscillator Design Using Current-Mirrors,” in 2018 41st International Conference on Telecommunications and Signal Processing (TSP), 2018, doi: 10.1109/TSP.2018.8441399.
  43. V. Tenentes, D. Rossi, and B. M. Al-Hashimi, “Collective-Aware System-on-Chips for Dependable IoT Applications,” in 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2018, pp. 57–60, doi: 10.1109/IOLTS.2018.8474172.
  44. J. R. B. Bantock, V. Tenentes, B. M. Al-Hashimi, and G. V. Merrett, “Online Tuning of Dynamic Power Management for Efficient Execution of Interactive Workloads,” in 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017, doi: 10.1109/ISLPED.2017.8009195.
  45. H. Herencsar, A. Kartci, J. Koton, G. Tsirimokou, and C. Psychalinos, “Voltage Gain-Controlled Third-Generation Current Conveyor and Its All-Pass Filter Verification,” in 2017 European Conference on Circuit Theory and Design (ECCTD), 2017, doi: 10.1109/ECCTD.2017.8093273.
  46. A. Kartci et al., “Fractional-Order Oscillator Design Using Unity-Gain Voltage Buffers and OTAs,” in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, pp. 555–558, doi: 10.1109/MWSCAS.2017.8052983.
  47. M. D. Gutierrez, V. Tenentes, T. J. Kazmierski, and D. Rossi, “Low Cost Error Monitoring for Improved Maintainability of IoT Applications,” in 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2017, pp. 1–6, doi: 10.1109/DFT.2017.8244445.
  48. M. D. Gutierrez, V. Tenentes, T. J. Kazmierski, and D. Rossi, “Low Power Probabilistic Online Monitoring of Systematic Erroneous Behaviour,” in 2017 IEEE European Test Symposium (ETS), 2017, doi: 10.1109/ETS.2017.7968239.
  49. S.-G. Papadopoulos, V. Gerakis, Y. Tsiatouhas, and A. Hatzopoulos, “Oscillation-Based Technique for Post-Bond Parallel Testing and Diagnosis of Multiple TSVs,” in 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017, pp. 1–6, doi: 10.1109/PATMOS.2017.8106985.
  50. Y. Sfikas and Y. Tsiatouhas, “BTI and HCI Degradation Detection in SRAM Cells,” in 2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2017, doi: 10.1109/MOCAST.2017.7937664.
  51. Y. Sfikas and Y. Tsiatouhas, “Variation Tolerant BTI Monitoring in SRAM Cells,” in 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, pp. 100–105, doi: 10.1109/IOLTS.2017.8046203.
  52. Y. Tsiatouhas, “Periodic Bias-Temperature Instability Monitoring in SRAM Cells,” in 2017 IEEE European Test Symposium (ETS), 2017, doi: 10.1109/ETS.2017.7968221.
  53. G. Tsirimokou, C. Psychalinos, and A. Elwakil, “Analysis and Experimental Verification of a Fractional-Order Hartley Oscillator,” in 2017 European Conference on Circuit Theory and Design (ECCTD), 2017, doi: 10.1109/ECCTD.2017.8093312.
  54. G. Tsirimokou, R. Sotner, J. Jerabek, J. Koton, and C. Psychalinos, “Programmable Analog Array of Fractional-Order Filters with CFOAs,” in 2017 40th International Conference on Telecommunications and Signal Processing (TSP), 2017, pp. 706–709, doi: 10.1109/TSP.2017.8076079.
  55. G. Tsirimokou, A. Kartci, J. Koton, N. Herencsar, and C. Psychalinos, “Comparative Study of Fractional-Order Differentiators and Integrators,” in 2017 40th International Conference on Telecommunications and Signal Processing (TSP), 2017, pp. 714–717, doi: 10.1109/TSP.2017.8076081.
  56. C. Vastarouchas, G. Tsirimokou, T. Freeborn, C. Psychalinos, and A. Elwakil, “Design of a Wood Tissue Impedance Emulator in Monolithic Form,” in 2017 European Conference on Circuit Theory and Design (ECCTD), 2017, doi: 10.1109/ECCTD.2017.8093305.
  57. V. Tenentes et al., “Hardware and Software Innovations in Energy-Efficient System-Reliability Monitoring,” in 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2017, pp. 1–5, doi: 10.1109/DFT.2017.8244435.
  58. F. Vartziotis and X. Kavousianos, “Critical Path – Oriented & Thermal Aware X-Filling for High Un-Modeled Defect Coverage,” in 2017 Design, Automation and Test in Europe (DATE), 2017, pp. 642–645, doi: 10.23919/DATE.2017.7927067.
  59. J. Liaperdos, A. Arapoyanni, and Y. Tsiatouhas, “Improved Alternate Test Accuracy Using Weighted Training Sets,” in 2016 Conference on Design of Circuits and Integrated Systems (DCIS), 2017, pp. 1–6, doi: 10.1109/DCIS.2016.7845263.
  60. M. R. Bar, N. Kant, F. A. Khanday, G. Tsirimokou, and C. Psychalinos, “Design of Fractional-Order Multiphase Sinusoidal Oscillators,” in IET Conference Publications, 2016, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85047922940&partnerID=40&md5=655fa0bd874266aadb935218dfd5e670.
  61. H. Chahal, V. Tenentes, D. Rossi, and B. M. Al-Hashimi, “BTI Aware Thermal Management for Reliable DVFS Designs,” in 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016, pp. 1–6, doi: 10.1109/DFT.2016.7684059.
  62. I. Dimeas, G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Experimental Verification of Filters Using Fractional-Order Capacitor and Inductor Emulators,” in 2016 39th International Conference on Telecommunications and Signal Processing (TSP), 2016, pp. 559–562, doi: 10.1109/TSP.2016.7760943.
  63. P. Georgiou, F. Vartziotis, X. Kavousianos, and K. Chakrabarty, “Two-Dimensional Time-Division Multiplexing for 3D-SoCs,” in 2016 IEEE European Test Symposium (ETS), 2016, doi: 10.1109/ETS.2016.7519312.
  64. M. D. Gutierrez, V. Tenentes, and T. J. Kazmierski, “Susceptible Workload Driven Selective Fault Tolerance Using a Probabilistic Fault Model,” in 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2016, pp. 115–120, doi: 10.1109/IOLTS.2016.7604682.
  65. R. Katreepalli, H. Chemanchula, T. Haniotakis, and Y. Tsiatouhas, “Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, pp. 367–372, doi: 10.1109/ISVLSI.2016.34.
  66. J. Liaperdos, A. Arapoyanni, and Y. Tsiatouhas, “Optimized Built-in Self-Calibration of RF SoCs,” in 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016, doi: 10.1109/MOCAST.2016.7495112.
  67. Y. Sfikas and Y. Tsiatouhas, “NLTF Based BIST Circuit for DRAM Testing,” in 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016, doi: 10.1109/MOCAST.2016.7495144.
  68. S. Valadimas, A. Arapoyanni, and Y. Tsiatouhas, “Timing Error Mitigation in Microprocessor Cores,” in 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2016, pp. 772–775, doi: 10.1109/ICECS.2016.7841316.
  69. G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Switched-Current Fractional-Order Filter Designs,” in Proceedings – IEEE International Symposium on Circuits and Systems, 2016, pp. 682–685, doi: 10.1109/ISCAS.2016.7527332.
  70. A. Anastasiou, Y. Tsiatouhas, and A. Arapoyanni, “On the Reuse of Existing Error Tolerance Circuitry for Low Power Scan Testing,” in Proceedings – IEEE International Symposium on Circuits and Systems, 2015, pp. 1578–1581, doi: 10.1109/ISCAS.2015.7168949.
  71. H.-M. Dounavi, Y. Tsiatouhas, and A. Arapoyanni, “Scan Chain Based At-Speed Diagnosis in the Presence of Scan Output Compaction Schemes,” in ACM International Conference Proceeding Series, 2015, pp. 419–423, doi: 10.1145/2801948.2801956.
  72. K. Katsarou and Y. Tsiatouhas, “Soft Error Immune Latch Under SEU Related Double-Node Charge Collection,” in Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS), 2015, pp. 46–49, doi: 10.1109/IOLTS.2015.7229830.
  73. J. Liaperdos, A. Arapoyanni, and Y. Tsiatouhas, “A Method for the Estimation of Defect Detection Probability of Analog/RF Defect-Oriented Tests,” in Proceedings – Design, Automation and Test in Europe (DATE), 2015, pp. 1395–1400, doi: 10.7873/date.2015.0617.
  74. J. Liaperdos, H.-G. Stratigopoulos, L. Abdallah, Y. Tsiatouhas, A. Arapoyanni, and X. Li, “Fast Deployment of Alternate Analog Test Using Bayesian Model Fusion,” in Proceedings – Design, Automation and Test in Europe (DATE), 2015, pp. 1030–1035, doi: 10.7873/date.2015.0102.
  75. D. Rossi, V. Tenentes, S. Khursheed, and B. M. Al-Hashimi, “BTI and Leakage Aware Dynamic Voltage Scaling for Reliable Low Power Cache Memories,” in Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS), 2015, pp. 194–199, doi: 10.1109/IOLTS.2015.7229858.
  76. D. Rossi, V. Tenentes, S. Khursheed, and B. M. Al-Hashimi, “NBTI and Leakage Aware Sleep Transistor Design for Reliable and Energy Efficient Power Gating,” in 2015 IEEE European Test Symposium (ETS), 2015, doi: 10.1109/ETS.2015.7138752.
  77. Y. Sfikas and Y. Tsiatouhas, “On Resistive Open Defect Detection in DRAMs: The Charge Accumulation Effect,” in 2015 IEEE European Test Symposium (ETS), 2015, doi: 10.1109/ETS.2015.7138747.
  78. V. Tenentes, D. Rossi, S. Khursheed, and B. M. Al-Hashimi, “Diagnosis of Power Switches with Power-Distribution-Network Consideration,” in 2015 IEEE European Test Symposium (ETS), 2015, doi: 10.1109/ETS.2015.7138774.
  79. G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, “Digitally Programmed Fractional-Order Chebyshev Filters Realizations Using Current-Mirrors,” in Proceedings – IEEE International Symposium on Circuits and Systems, 2015, pp. 2337–2340, doi: 10.1109/ISCAS.2015.7169152.
  80. K. Roumelioti, G. Tsirimokou, and C. Psychalinos, “Ultra-Low Voltage Analog Pre-Processing Stage for Realizing the Pan-Tompkins Algorithm,” Journal of Low Power Electronics, vol. 11, no. 3, pp. 308–315, Sep. 2015, doi: 10.1166/jolpe.2015.1394.
  81. F. Vartziotis, X. Kavousianos, and K. Chakrabarty, “A Branch-&-Bound Algorithm for TAM Optimization in Multi-Vdd SoCs,” in 2015 IEEE European Test Symposium (ETS), 2015, doi: 10.1109/ETS.2015.7138746.
  82. A. Anastasiou and Y. Tsiatouhas, “Power Efficient Scan Testing by Exploiting Existing Error Tolerance Circuitry in a Design,” in 2014 IEEE European Test Symposium (ETS), 2014, doi: 10.1109/ETS.2014.6847834.
  83. H.-M. Dounavi and Y. Tsiatouhas, “Stuck-at Fault Diagnosis in Scan Chains,” in 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2014, doi: 10.1109/DTIS.2014.6850663.
  84. K. Katsarou and Y. Tsiatouhas, “Double Node Charge Sharing SEU Tolerant Latch Design,” in 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014, pp. 122–127, doi: 10.1109/IOLTS.2014.6873683.
  85. X. Kavousianos and K. Chakrabarty, “Recent Advances in Single- and Multi-Site Test Optimization for DVS-Based SoCs,” in 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2014, doi: 10.1109/DTIS.2014.6850675.
  86. F. Vartziotis, X. Kavousianos, K. Chakrabarty, R. Parekhji, and A. Jain, “Multi-Site Test Optimization for Multi-Vdd SoCs Using Space- and Time-Division Multiplexing,” in 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, doi: 10.7873/DATE2014.141.
  87. R. Wang, Z. Zhang, X. Kavousianos, Y. Tsiatouhas, and K. Chakrabarty, “Built-in Self-Test, Diagnosis, and Repair of Multimode Power Switches,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 8, pp. 1231–1244, Aug. 2014, doi: 10.1109/TCAD.2014.2314303.
  88. A. Efthymiou, “An Error Tolerant CAM with NAND Match-Line Organization,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2013, pp. 257–262, doi: 10.1145/2483028.2483105.
  89. X. Kavousianos and K. Chakrabarty, “Testing for SoCs with Advanced Static and Dynamic Power-Management Capabilities,” in 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, pp. 737–742, doi: 10.7873/DATE.2013.158.
  90. K. Katsarou, Y. Tsiatouhas, and A. Arapoyanni, “NBTI Aging Tolerance in Pipeline Based Designs,” in 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013, pp. 31–36, doi: 10.1109/IOLTS.2013.6604047.
  91. J. Liaperdos, A. Arapoyanni, and Y. Tsiatouhas, “A Test and Calibration Strategy for Adjustable RF Circuits,” Analog Integrated Circuits and Signal Processing, vol. 74, no. 1, pp. 175–192, Jan. 2013, doi: 10.1007/s10470-012-9981-x.
  92. E. Arvaniti and Y. Tsiatouhas, “Low Power Scan by Partitioning and Scan Hold,” in 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2012, pp. 262–265, doi: 10.1109/DDECS.2012.6219070.
  93. M. Chalkia and Y. Tsiatouhas, “The Leafs Scan-Chain for Test Application Time and Scan Power Reduction,” in 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012, pp. 749–752, doi: 10.1109/ICECS.2012.6463646.
  94. L. Dermetzoglou, J. Liaperdos, A. Arapoyanni, and Y. Tsiatouhas, “Testing Wireless Transceivers’ RF Front-Ends Utilizing Defect-Oriented BIST Techniques,” in 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012, pp. 961–964, doi: 10.1109/ICECS.2012.6463501.
  95. X. Kavousianos, K. Chakrabarty, A. Jain, and R. Parekhji, “Time-Division Multiplexing for Testing SoCs with DVS and Multiple Voltage Islands,” in 2012 IEEE European Test Symposium (ETS), 2012, doi: 10.1109/ETS.2012.6233019.
  96. S. Valadimas, Y. Tsiatouhas, and A. Arapoyanni, “Cost and Power Efficient Timing Error Tolerance in Flip-Flop Based Microprocessor Cores,” in 2012 IEEE European Test Symposium (ETS), 2012, doi: 10.1109/ETS.2012.6233002.
  97. S. Valadimas, Y. Tsiatouhas, A. Arapoyanni, and A. Evans, “Single Event Upset Tolerance in Flip-Flop Based Microprocessor Cores,” in Proceedings – IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2012, pp. 79–84, doi: 10.1109/DFT.2012.6378204.
  98. I. Voyiatzis, C. Efstathiou, Y. Tsiatouhas, and C. Sgouropoulou, “A Novel Architecture to Reduce Test Time in March-Based SRAM Tests,” in 2012 7th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012, doi: 10.1109/DTIS.2012.6232963.
  99. I. Liaperdos, L. Dermentzoglou, A. Arapoyanni, and Y. Tsiatouhas, “A Test Technique and a BIST Circuit to Detect Catastrophic Faults in RF Mixers,” in 2011 6th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011, doi: 10.1109/DTIS.2011.5941433.
  100. X. Kavousianos and K. Chakrabarty, “Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands,” in Proceedings of the Asian Test Symposium, 2011, pp. 33–39, doi: 10.1109/ATS.2011.53.
  101. Z. Owda, Y. Tsiatouhas, and T. Haniotakis, “High Performance and Low Power Dynamic Circuit Design,” in 2011 IEEE 9th International New Circuits and Systems Conference (NEWCAS), 2011, pp. 502–505, doi: 10.1109/NEWCAS.2011.5981329.
  102. V. Tenentes and X. Kavousianos, “Test-Data Volume and Scan-Power Reduction with Low ATE Interface for Multi-Core SoCs,” in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (ICCAD), 2011, pp. 747–754, doi: 10.1109/ICCAD.2011.6105413.
  103. V. Tenentes and X. Kavousianos, “Low Power Test-Compression for High Test-Quality and Low Test-Data Volume,” in Proceedings of the Asian Test Symposium, 2011, pp. 46–53, doi: 10.1109/ATS.2011.75.
  104. Z. Zhang, X. Kavousianos, Y. Tsiatouhas, and K. Chakrabarty, “A BIST Scheme for Testing and Repair of Multi-Mode Power Switches,” in Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium (IOLTS), 2011, pp. 115–120, doi: 10.1109/IOLTS.2011.5993821.
  105. Z. Zhang, X. Kavousianos, K. Chakrabarty, and Y. Tsiatouhas, “A Robust and Reconfigurable Multi-Mode Power Gating Architecture,” in Proceedings of the IEEE International Conference on VLSI Design, 2011, pp. 280–285, doi: 10.1109/VLSID.2011.29.
  106. Z. Zhang, X. Kavousianos, Y. Luo, Y. Tsiatouhas, and K. Chakrabarty, “Signature Analysis for Testing, Diagnosis, and Repair of Multi-Mode Power Switches,” in Proceedings – 16th IEEE European Test Symposium (ETS), 2011, pp. 13–18, doi: 10.1109/ETS.2011.18.
  107. S. Balatsouka, V. Tenentes, X. Kavousianos, and K. Chakrabarty, “Defect Aware X-Filling for Low-Power Scan Testing,” in Proceedings – Design, Automation and Test in Europe (DATE), 2010, pp. 873–878, doi: 10.1109/date.2010.5456928.
  108. L. Dermentzoglou, A. Arapoyanni, and Y. Tsiatouhas, “A Build-in Self-Test Technique for RF Mixers,” in Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010, pp. 88–92, doi: 10.1109/DDECS.2010.5491810.
  109. P. D. Ferguson, A. Efthymiou, T. Arslan, and D. Hume, “Optimising Self-Timed FPGA Circuits,” in Proceedings – 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), 2010, pp. 563–570, doi: 10.1109/DSD.2010.97.
  110. T. Haniotakis, Z. Owda, and Y. Tsiatouhas, “Memory-less Pipeline Dynamic Circuit Design Technique,” in Proceedings – IEEE Annual Symposium on VLSI (ISVLSI), 2010, pp. 201–205, doi: 10.1109/ISVLSI.2010.42.
  111. X. Kavousianos, K. Chakrabarty, E. Kalligeros, and V. Tenentes, “Defect Coverage-Driven Window-Based Test Compression,” in Proceedings of the Asian Test Symposium, 2010, pp. 141–146, doi: 10.1109/ATS.2010.33.
  112. Y. Moisiadis and Y. Tsiatouhas, “A Receiver Circuit for Low-Swing Interconnect Schemes,” in Proceedings – IEEE Annual Symposium on VLSI (ISVLSI), 2010, pp. 238–241, doi: 10.1109/ISVLSI.2010.41.
  113. S. Valadimas, Y. Tsiatouhas, and A. Arapoyanni, “Timing Error Tolerance in Nanometer ICs,” in Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium (IOLTS), 2010, pp. 283–288, doi: 10.1109/IOLTS.2010.5560189.
  114. V. Tenentes and X. Kavousianos, “Self-Freeze Linear Decompressors for Low Power Testing,” in Proceedings – IEEE Annual Symposium on VLSI (ISVLSI), 2010, pp. 63–68, doi: 10.1109/ISVLSI.2010.37.
  115. D. Koppad and A. Efthymiou, “BIST for Strongly-Indicating Asynchronous Circuits,” in Proceedings – 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), 2009, pp. 215–218, doi: 10.1109/VLSISOC.2009.6041359.
  116. X. Kavousianos and K. Chakrabarty, “Generation of Compact Test Sets with High Defect Coverage,” in Proceedings – Design, Automation and Test in Europe (DATE), 2009, pp. 1130–1135, doi: 10.1109/date.2009.5090833.
  117. M. Koutsoupia, E. Kalligeros, X. Kavousianos, and D. Nikolos, “LFSR-Based Test-Data Compression with Self-Stoppable Seeds,” in Proceedings – Design, Automation and Test in Europe (DATE), 2009, pp. 1482–1487, doi: 10.1109/date.2009.5090897.
  118. Y. Sfikas and Y. Tsiatouhas, “Physical Design Oriented DRAM Neighborhood Pattern Sensitive Fault Testing,” in Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2009, pp. 108–113, doi: 10.1109/DDECS.2009.5012108.
  119. V. Tenentes, X. Kavousianos, and E. Kalligeros, “State Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores,” in Proceedings – Design, Automation and Test in Europe (DATE), 2008, pp. 474–479, doi: 10.1109/DATE.2008.4484726.
  120. D. P. Vasudevan and A. Efthymiou, “A Partial Scan Based Test Generation for Asynchronous Circuits,” in Proceedings – 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2008, pp. 186–189, doi: 10.1109/DDECS.2008.4538783.
  121. R. Hassan, A. Harris, N. Topham, and A. Efthymiou, “Synthetic Trace-Driven Simulation of Cache Memory,” in Proceedings – 21st International Conference on Advanced Information Networking and Applications Workshops/Symposia (AINAW’07), 2007, vol. 2, pp. 764–771, doi: 10.1109/AINAW.2007.345.
  122. L. Dermentzoglou, A. Karagounis, A. Arapoyanni, and Y. Tsiatouhas, “An Embedded Test Circuit for RF Single Ended Low Noise Amplifiers,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2007, pp. 1119–1122, doi: 10.1109/ICECS.2007.4511191.
  123. A. Efthymiou, “Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits,” in Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2007, pp. 377–382, doi: 10.1109/DDECS.2007.4295316.
  124. Y. Tsiatouhas, A. Arapoyanni, and D. Skias, “A Scan Flip-Flop for Low-Power Scan Operation,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2007, pp. 439–442, doi: 10.1109/ICECS.2007.4511024.
  125. A. Floros, Y. Tsiatouhas, A. Arapoyanni, and Th. Haniotakis, “A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2006, pp. 692–695, doi: 10.1109/ICECS.2006.379883.
  126. X. Kavousianos, E. Kalligeros, and D. Nikolos, “Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding,” in Proceedings – Design, Automation and Test in Europe (DATE), 2006, vol. 1, doi: 10.1109/date.2006.243926.
  127. E. Kalligeros, X. Kavousianos, and D. Nikolos, “Efficient Multiphase Test Set Embedding for Scan-Based Testing,” in Proceedings – International Symposium on Quality Electronic Design (ISQED), 2006, pp. 433–438, doi: 10.1109/ISQED.2006.56.
  128. Y. Tsiatouhas and A. Arapoyanni, “High Fan-in Differential Current Mirror Logic,” in Proceedings – IEEE International Symposium on Circuits and Systems, 2006, pp. 3894–3897, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-34547278789&partnerID=40&md5=9210af97d6f83e37083b0f6eb87efb79.
  129. M. Amde, T. Felicijan, A. Efthymiou, D. Edwards, and L. Lavagno, “Asynchronous On-Chip Networks,” IEE Proceedings: Computers and Digital Techniques, vol. 152, no. 2, pp. 273–283, Mar. 2005, doi: 10.1049/ip-cdt:20045093.
  130. L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Built-in Self-Test Scheme for Differential Ring Oscillators,” in Proceedings – International Symposium on Quality Electronic Design (ISQED), 2005, pp. 448–452, doi: 10.1109/ISQED.2005.2.
  131. A. Efthymiou, J. D. Garside, and I. Papaefstathiou, “A Low-Power Processor Architecture Optimized for Wireless Devices,” in Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, 2005, pp. 185–190, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-24944515538&partnerID=40&md5=0c729767f5d5f699da7c010093e89b71.
  132. G. Gekas, D. Nikolos, E. Kalligeros, and X. Kavousianos, “Power Aware Test-Data Compression for Scan-Based Testing,” in 12th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2005, doi: 10.1109/ICECS.2005.4633432.
  133. E. Kalligeros, D. Kaseridis, X. Kavousianos, and D. Nikolos, “Reseeding-Based Test Set Embedding with Reduced Test Sequences,” in Proceedings – International Symposium on Quality Electronic Design (ISQED), 2005, pp. 226–231, doi: 10.1109/ISQED.2005.105.
  134. S. Matakias, Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni, and A. Efthymiou, “Fast, Parallel Two-Rail Code Checker with Enhanced Testability,” in Proceedings – 11th IEEE International On-Line Testing Symposium (IOLTS), 2005, pp. 149–156, doi: 10.1109/IOLTS.2005.29.
  135. S. Matakias, Y. Tsiatouhas, A. Arapoyanni, and Th. Haniotakis, “An Embedded IDDQ Testing Circuit and Technique,” in Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference, 2005, pp. 471–474, doi: 10.1109/ESSCIR.2005.1541662.
  136. S. Matakias, Y. Tsiatouhas, A. Arapoyanni, and Th. Haniotakis, “An Embedded IDDQ Testing Circuit and Technique,” in 12th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2005, doi: 10.1109/ICECS.2005.4633505.
  137. A. Rao, Th. Haniotakis, Y. Tsiatouhas, and H. Djemil, “The Use of Pre-Evaluation Phase in Dynamic CMOS Logic,” in Proceedings – IEEE Computer Society Annual Symposium on VLSI – New Frontiers in VLSI, 2005, pp. 270–271, doi: 10.1109/ISVLSI.2005.72.
  138. Y. Tsiatouhas, K. Limniotis, A. Arapoyanni, and Th. Haniotakis, “A Low Power NORA Circuit Design Technique Based on Charge Recycling,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2003, vol. 1, pp. 224–227, doi: 10.1109/ICECS.2003.1302017.
  139. L. Denmentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Novel Scheme for Testing Radio Frequency Voltage Controlled Oscillators,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2003, vol. 2, pp. 595–598, doi: 10.1109/ICECS.2003.1301855.
  140. A. Efthymiou and J. D. Garside, “Adaptive Pipeline Structures for Speculation Control,” in Proceedings – International Symposium on Asynchronous Circuits and Systems, 2003, pp. 46–55, doi: 10.1109/ASYNC.2003.1199165.
  141. A. Efthymiou, J. Bainbridge, and D. A. Edwards, “Adding Testability to an Asynchronous Interconnect for GALS SoC,” in Proceedings of the Asian Test Symposium, 2004, pp. 20–23, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-13244281565&partnerID=40&md5=038c650832c8de44cbc897cd5adb9612.
  142. A. Efthymiou, C. Sotiriou, and D. Edwards, “Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits,” in Proceedings – Design, Automation and Test in Europe Conference and Exhibition, 2004, vol. 1, pp. 672–673, doi: 10.1109/DATE.2004.1268924.
  143. A. Efthymiou, W. Suntiamorntut, J. Garside, and L. E. M. Brackenbury, “An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm,” in Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2004, pp. 207–215, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-2942683152&partnerID=40&md5=e4e8b7817ed4a70d2fa214c1aa8063c6.
  144. E. Kalligeros, X. Kavousianos, and D. Nikolos, “A ROMless LFSR Reseeding Scheme for Scan-Based BIST,” in Proceedings of the Asian Test Symposium, 2002, pp. 206–211, doi: 10.1109/ATS.2002.1181712.
  145. E. Kalligeros, X. Kavousianos, and D. Nikolos, “A Highly Regular Multi-Phase Reseeding Technique for Scan-Based BIST,” in Proceedings of the IEEE Great Lakes Symposium on VLSI, 2003, pp. 295–298, doi: 10.1145/764883.764885.
  146. E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, “An Efficient Seeds Selection Method for LFSR-Based Test-Per-Clock BIST,” in Proceedings – International Symposium on Quality Electronic Design (ISQED), 2002, pp. 261–266, doi: 10.1109/ISQED.2002.996747.
  147. E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, “A New Reseeding Technique for LFSR-Based Test Pattern Generation,” in Proceedings – 7th International On-Line Testing Workshop (IOLTW), 2001, pp. 80–86, doi: 10.1109/OLT.2001.937823.
  148. X. Kavousianos and D. Nikolos, “Virtual-Scan: A Novel Approach for Software-Based Self-Testing of Microprocessors,” in Proceedings – IEEE International Symposium on Circuits and Systems, 2003, vol. 5, pp. V237–V240, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-0038758734&partnerID=40&md5=bfdb4daa9bc082042340c0b0c4c6a3e7.
  149. S. Matakias, Y. Tsiatouhas, A. Arapoyanni, and Th. Haniotakis, “A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 20, no. 5, pp. 523–531, Oct. 2004, doi: 10.1023/B:JETT.0000042516.12841.36.
  150. S. Matakias, Y. Tsiatouhas, Th. Haniotakis, and A. Arapoyanni, “Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-in Applications,” in Proceedings – IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, 2004, pp. 293–296, doi: 10.1109/ISVLSI.2004.1339562.
  151. M. Bellos, D. Bakalis, D. Nikolos, and X. Kavousianos, “Low Power Testing by Test Vector Ordering with Vector Repetition,” in Proceedings – 5th International Symposium on Quality Electronic Design (ISQED), 2004, pp. 205–210, doi: 10.1109/ISQED.2004.1283674.
  152. A. Rao, T. Haniotakis, Y. Tsiatouhas, and V. Kaky, “A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations,” in Proceedings – 10th IEEE International On-Line Testing Symposium (IOLTS), 2004, pp. 52–57, doi: 10.1109/OLT.2004.1319659.
  153. Y. Tsiatouhas, Th. Haniotakis, and A. Arapoyanni, “An Embedded IDDQ Testing Architecture and Technique,” in Proceedings – International Symposium on Quality Electronic Design (ISQED), 2003, pp. 442–445, doi: 10.1109/ISQED.2003.1194773.
  154. Y. Tsiatouhas, Th. Haniotakis, A. Chrisanthopoulos, and A. Arapoyanni, “A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing,” in Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW), 2002, pp. 56–60, doi: 10.1109/OLT.2002.1030184.
  155. Y. Tsiatouhas, S. Matakias, A. Arapoyanni, and Th. Haniotakis, “A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs,” in Proceedings – 9th IEEE International On-Line Testing Symposium (IOLTS), 2003, pp. 12–16, doi: 10.1109/OLT.2003.1214360.
  156. A. Chrisanthopoulos, Y. Moisiadis, A. Varagis, Y. Tsiatouhas, and A. Arapoyanni, “A New Flash Memory Sense Amplifier in 0.18μm CMOS Technology,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2001, vol. 2, pp. 941–944, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-13444296772&partnerID=40&md5=6619c22d7474d462e0d6819188639263.
  157. A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, and A. Arapoyanni, “New Test Pattern Generation Units for NPSF Oriented Memory Built-in Self Test,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2001, vol. 2, pp. 749–752, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-0012022257&partnerID=40&md5=cb2826d9c1395513fcd1e701df21c77d.
  158. A. Chrisanthopoulos, G. Kamoulakos, Y. Tsiatouhas, and A. Arapoyanni, “A Test Pattern Generation Unit for Memory NPSF Built-in Self Test,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2000, vol. 1, pp. 425–428, doi: 10.1109/ICECS.2000.911571.
  159. A. Efthymiou and J. D. Garside, “An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks,” in Proceedings of the International Symposium on Low Power Electronics and Design, 2002, pp. 136–141, doi: 10.1109/lpe.2002.146726.
  160. A. Efthymiou and J. D. Garside, “A CAM With Mixed Serial-Parallel Comparison for Use in Low Energy Caches,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 3, pp. 325–329, Mar. 2004, doi: 10.1109/TVLSI.2004.824298.
  161. A. Efthymiou and J. D. Garside, “Adaptive Pipeline Depth Control for Processor Power-Management,” in Proceedings – IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002, pp. 454–457, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-0036396969&partnerID=40&md5=a0bbb4d5e4b79f3a3653337361202524.
  162. T. Haniotakis, Y. Tsiatouhas, D. Nikolos, and C. Efstathiou, “Concurrent Detection of Soft Errors Based on Current Monitoring,” in Proceedings – 7th International On-Line Testing Workshop (IOLTW), 2001, pp. 106–110, doi: 10.1109/OLT.2001.937828.
  163. X. Kavousianos, D. Bakalis, and D. Nikolos, “A Novel Reseeding Technique for Accumulator-Based Test Pattern Generation,” in Proceedings of the IEEE Great Lakes Symposium on VLSI, 2001, pp. 7–12, doi: 10.1145/368122.368145.
  164. X. Kavousianos, D. Bakalis, M. Bellos, and D. Nikolos, “An Efficient Test Vector Ordering Method for Low Power Testing,” in Proceedings – IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, 2004, pp. 285–288, doi: 10.1109/ISVLSI.2004.1339559.
  165. D. Skias, Th. Haniotakis, Y. Tsiatouhas, and A. Arapoyanni, “A State Assignment Algorithm for Finite State Machines,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2000, vol. 2, pp. 823–826, doi: 10.1109/ICECS.2000.913003.
  166. S. J. Piestrak, D. Bakalis, and X. Kavousianos, “On the Design of Self-Testing Checkers for Modified Berger Codes,” in Proceedings – 7th International On-Line Testing Workshop (IOLTW), 2001, pp. 153–157, doi: 10.1109/OLT.2001.937835.
  167. Y. Tsiatouhas, Th. Haniotakis, D. Nicolos, and A. Arapoyanni, “Extending the Viability of IDDQ Testing in the Deep Submicron Era,” in Proceedings – International Symposium on Quality Electronic Design (ISQED), 2002, pp. 100–105, doi: 10.1109/ISQED.2002.996706.
  168. Y. Tsiatouhas, A. Chrisanthopoulos, G. Kamoulakos, and Th. Haniotakis, “New Memory Sense Amplifier Designs in CMOS Technology,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2000, vol. 1, pp. 19–22, doi: 10.1109/ICECS.2000.911469.
  169. Y. Tsiatouhas, Y. Moisiadis, Th. Haniotakis, D. Nikolos, and A. Arapoyanni, “A New Scheme for Effective IDDQ Testing in Deep Submicron,” in Proceedings – 2000 IEEE International Workshop on Defect Based Testing, 2000, pp. 9–14, doi: 10.1109/DBT.2000.843684.
  170. Y. Tsiatouhas, Th. Haniotakis, and D. Nikolos, “A Compact Built-in Current Sensor for IDDQ Testing,” in Proceedings – 6th IEEE International On-Line Testing Workshop, 2000, pp. 95–99, doi: 10.1109/OLT.2000.856619.
  171. Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, and C. Efstathiou, “On Testability of Multiple Precharged Domino Logic,” in Proceedings – International Symposium on Quality Electronic Design (ISQED), 2000, pp. 299–303, doi: 10.1109/ISQED.2000.838886.
  172. D. Bakalis, D. Nikolos, and X. Kavousianos, “Test Response Compaction by an Accumulator Behaving as a Multiple Input Non-Linear Feedback Shift Register,” in IEEE International Test Conference (TC), 2000, pp. 804–811, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-0034480139&partnerID=40&md5=37ae259d15e3a5866c9800c0ace8eb9d.
  173. D. Bakalis, H. T. Vergos, D. Nikolos, X. Kavousianos, and G. Ph. Alexiou, “Low Power Dissipation in BIST Schemes for Modified Booth Multipliers,” in Proceedings – 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 1999, pp. 121–129, doi: 10.1109/DFTVS.1999.802877.
  174. G. Dimitrakopoulos, X. Kavousianos, and D. Nikolas, “Virtual-Scan: A Novel Approach for Software-Based Self-Testing of Microprocessors,” in Proceedings – IEEE International Symposium on Circuits and Systems, 2003, vol. 5, pp. V237–V240, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-0038758734&partnerID=40&md5=bfdb4daa9bc082042340c0b0c4c6a3e7.
  175. T. Haniotakis, Y. Tsiatouhas, D. Nikolos, and A. Arapoyanni, “A Versatile Built-in Self Test Scheme for Delay Fault Testing,” in Proceedings – Design, Automation and Test in Europe (DATE), 2000, p. 756, doi: 10.1109/DATE.2000.840889.
  176. T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropulos, Y. Tsiatouhas, and H. T. Vergos, “A Class of Easily Path Delay Fault Testable Circuits,” in 2000 Southwest Symposium on Mixed-Signal Design (SSMSD), 2000, pp. 165–170, doi: 10.1109/SSMSD.2000.836466.
  177. D. Nikolos, T. Haniotakis, H. T. Vergos, and Y. Tsiatouhas, “Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks,” in Proceedings – Design, Automation and Test in Europe (DATE), 1999, pp. 112–116, doi: 10.1109/DATE.1999.761105.
  178. H. T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, and M. Nicolaidis, “On Path Delay Fault Testing of Multiplexer – Based Shifters,” in Proceedings of the IEEE Great Lakes Symposium on VLSI, 1999, pp. 20–23, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-0033361728&partnerID=40&md5=078e3452008c8bd552e66810d3a8b6aa.
  179. Y. Tsiatouhas and Th. Haniotakis, “Zero Aliasing Built-in Self Test Technique for Delay Fault Testing,” in IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1999, pp. 95–100, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-0033339776&partnerID=40&md5=c51297d757e5ba54d001848b5c1d154b.
  180. X. Kavousianos, D. Nikolos, and S. Tragoudas, “On-Chip Deterministic Counter-Based TPG with Low Heat Dissipation,” in 1999 Southwest Symposium on Mixed-Signal Design (SSMSD), 1999, pp. 87–92, doi: 10.1109/SSMSD.1999.768597.
  181. E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, “On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 18, no. 3, pp. 315–332, Jun. 2002, doi: 10.1023/A:1015039323168.
  182. X. Kavousianos and D. Nikolos, “Novel Single and Double Output TSC Berger Code Checkers,” in Proceedings of the IEEE VLSI Test Symposium, 1998, pp. 348–353, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-0032319934&partnerID=40&md5=52de71a5ae62f585db2473ce9380e64a.
  183. X. Kavousianos and D. Nikolos, “Self-Exercising Self-Testing k-Order Comparators,” in Proceedings of the IEEE VLSI Test Symposium, 1997, pp. 216–221, [Online]. Available: https://www.scopus.com/inward/record.uri?eid=2-s2.0-0030645004&partnerID=40&md5=b6fedffe0cc4a7cf4e0c3bf9feed5f68.
  184. X. Kavousianos, D. Nikolos, and G. Sidiropoulos, “Design of Compact and High Speed Totally Self-Checking CMOS Checkers for m-Out-of-n Codes,” in Proceedings – IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1997, pp. 128–136, doi: 10.1109/DFTVS.1997.628318.
  185. T. Haniotakis, Y. Tsiatouhas, D. Nikolos, and C. Efstathiou, “C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications,” in Proceedings – 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 1998, pp. 155–163, doi: 10.1109/DFTVS.1998.732162.
  186. M. Katevenis, P. Vatsolaki, and A. Efthymiou, “Pipelined Memory Shared Buffer for VLSI Switches,” in Proceedings of the Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication (SIGCOMM), 1995, pp. 39–48, doi: 10.1145/217382.217406.

Workshops

  • V. Tenentes and A. Papanikolaou “Interactive field-directed floorplan prototyping for 2D/3D IC’s ”, D43D: 4th Design for 3D Silicon Integration Workshop, June 25th-27th 2012, Lausanne.

    • PhD Dissertation

    V. Tenentes, Embedded Testing Architectures. PhD dissertation